Nitin Borkar

5.0k citations

37 papers · 3.1k indexed · 5 hit papers · h-index 19

Computer Networks and Communications top 0.5%
Hardware and Architecture top 0.2%
Electrical and Electronic Engineering top 2%
Electronic, Optical and Magnetic Materials top 10%
Biomedical Engineering

Co-authors: Yatin Hoskote Sriram Vangal Shekhar Borkar Saurabh Dighe Jason Howard Shailendra Jain James Tschanz Tiju Jacob
Topics: Low-power high-performance VLSI design (23 papers)Interconnection Networks and Systems (16 papers)Parallel Computing and Optimization Techniques (11 papers)
Cited by: Hardware and Architecture Computer Networks and Communications Electrical and Electronic Engineering
Journals: SHILAP Revista de lepidopterologíaIEEE Journal of Solid-State Circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partner nations: United States India Sweden

In The Last Decade

Nitin Borkar

36 papers receiving 2.9k citations

Hit Papers

5 papers align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

2007 474 citations Sriram Vangal, Jason Howard et al. profile →
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

2008 466 citations Sriram Vangal, Jason Howard et al. IEEE Journal of Solid-State Circuits profile →
A 5-GHz Mesh Interconnect for a Teraflops Processor

2007 416 citations Yatin Hoskote, Sriram Vangal et al. IEEE Micro profile →
A 5-GHz Mesh Interconnect for a Teraflops Processor

2007 415 citations Yatin Hoskote, Sriram Vangal et al. IEEE Micro profile →
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

2010 303 citations Jason Howard, Saurabh Dighe et al. IEEE Journal of Solid-State Circuits profile →

Peers

Countries citing papers authored by Nitin Borkar

Since Specialization

Citations

This map shows the geographic impact of Nitin Borkar's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Nitin Borkar with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Nitin Borkar more than expected).

Fields of papers citing papers by Nitin Borkar

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Nitin Borkar. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Nitin Borkar. The network helps show where Nitin Borkar may publish in the future.

Co-authorship network of co-authors of Nitin Borkar

This figure shows the co-authorship network connecting the top 25 collaborators of Nitin Borkar. A scholar is included among the top collaborators of Nitin Borkar based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Nitin Borkar. Nitin Borkar is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work	Indexed citations
1	Immediate Hemodynamic Changes during Slow Uninostril and Alternate Nostril Breathing Patterns in Normotensive Adults 2024 ·SHILAP Revista de lepidopterología ·(unknown),Nitin Borkar,(unknown),(unknown)	0
2	Efficacy and safety of oral tizanidine premedication as pre-emptive analgesia in adult patients undergoing elective surgeries- A systematic review 2023 ·Saudi Journal of Anaesthesia ·Abhijit Nair,(unknown),Nitin Borkar	1
3	Ultrasound-guided transversalis fascia plane block for postoperative analgesia: A systematic review and meta-analysis 2023 ·Indian Journal of Anaesthesia ·Abhijit Nair,(unknown),(unknown),Nitin Borkar	7
4	System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators 2016 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),Sang Phill Park,Dinesh Somasekhar,Young Moon Kim,Nitin Borkar,Ulya R. Karpuzcu,Chris H. Kim	11
5	Resiliency for many-core system on a chip 2014 ·Tanay Karnik,James Tschanz,Nitin Borkar,Jason Howard,Sriram Vangal,Vivek De,Shekhar Borkar	2
6	An IA-32 processor with a wide voltage operating range in 32nm CMOS 2012 ·(unknown),Saurabh Dighe,Shailendra Jain,(unknown),Satish Yada,(unknown),(unknown),(unknown),Sriram Muthukumar,(unknown),Arun Kumar,(unknown),R. Ramanarayanan,Vasantha Erraguntla,Jason Howard,Sriram Vangal,Paolo Aseron,(unknown),Nitin Borkar	1
7	A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping 2011 ·Saurabh Dighe,Sumeet Kumar Gupta,Vivek De,Sriram Vangal,Nitin Borkar,Shekhar Borkar,Kaushik Roy	12
8	Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor 2010 ·IEEE Journal of Solid-State Circuits ·Saurabh Dighe,Sriram Vangal,Paolo Aseron,Sachin Sharma Ashok Kumar,Tiju Jacob,Keith Bowman,Jason Howard,James Tschanz,Vasantha Erraguntla,Nitin Borkar,Vivek De,Shekhar Borkar	95
9	Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits 2009 ·IEEE Journal of Solid-State Circuits ·Muhammad Khellah,Nam Sung Kim,Yibin Ye,Dinesh Somasekhar,Tanay Karnik,Nitin Borkar,(unknown),Fatih Hamzaoglu,(unknown),Yuxiao Wang,Guomin Zhang,Clair Webb,Vivek De	17
10	An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOSbreakdown → 2008 ·IEEE Journal of Solid-State Circuits ·Sriram Vangal,Jason Howard,Greg Ruhl,Saurabh Dighe,H. Wilson,James Tschanz,D. Finan,(unknown),Tiju Jacob,Shailendra Jain,Vasantha Erraguntla,Clark Roberts,Yatin Hoskote,Nitin Borkar,Shekhar Borkar	466
11	A 5-GHz Mesh Interconnect for a Teraflops Processorbreakdown → 2007 ·IEEE Micro ·Yatin Hoskote,Sriram Vangal,(unknown),Nitin Borkar,Shekhar Borkar	415
12	An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOSbreakdown → 2007 ·Sriram Vangal,Jason Howard,(unknown),Saurabh Dighe,(unknown),James Tschanz,D. Finan,Prakash Iyer,(unknown),Tiju Jacob,Shailendra Jain,Sriram Venkataraman,Yatin Hoskote,Nitin Borkar	474
13	A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor 2007 ·IEEE Journal of Solid-State Circuits ·Muhammad Khellah,Dinesh Somasekhar,(unknown),Nam Sung Kim,Jason Howard,Greg Ruhl,(unknown),James Tschanz,Nitin Borkar,Fatih Hamzaoglu,(unknown),(unknown),Guomin Zhang,Vivek De	45
14	A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS 2006 ·Muhammad Khellah,Nam Sung Kim,Jason Howard,Greg Ruhl,(unknown),(unknown),(unknown),Dinesh Somasekhar,Nitin Borkar,(unknown),(unknown),(unknown),Kedong Zhang,Vivek De	23
15	A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization 2006 ·IEEE Journal of Solid-State Circuits ·Sriram Vangal,Yatin Hoskote,Nitin Borkar,Atila Alvandpour	49
16	5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS 2005 ·2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·(unknown),Nitin Borkar,Erik Seligman,(unknown),Vasantha Erraguntla,H. Wilson,(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),B. Bloechel,G. Dermer,(unknown),S. Narendra,(unknown),(unknown),Vivek De,Shekhar Borkar	1
17	A Six-Port 57GB/s Double-Pumped Nonblocking Router Core 2005 ·(unknown),Nitin Borkar,Atila Alvandpour	13
18	A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS 2003 ·Sriram Vangal,Yatin Hoskote,Dinesh Somasekhar,Vasantha Erraguntla,Jason Howard,Greg Ruhl,(unknown),D. Finan,Sanu Mathew,Nitin Borkar	15
19	A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS 2003 ·IEEE Journal of Solid-State Circuits ·Yatin Hoskote,B. Bloechel,G. Dermer,Vasantha Erraguntla,D. Finan,Jason Howard,(unknown),S. Narendra,Greg Ruhl,James Tschanz,Sriram Vangal,(unknown),H. Wilson,Jianzhong Xu,Nitin Borkar	30
20	A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes 2002 ·R. Nair,Nitin Borkar,(unknown),G. Dermer,(unknown),(unknown),(unknown),(unknown),(unknown),Erik Seligman,Sriram Vangal,(unknown)	14

About Nitin Borkar

Nitin Borkar is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering, having authored 37 papers that have together received 3.1k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (23 papers), Interconnection Networks and Systems (16 papers) and Parallel Computing and Optimization Techniques (11 papers). The work is most often cited by research in Hardware and Architecture (1.9k citations), Computer Networks and Communications (2.2k citations) and Electrical and Electronic Engineering (1.9k citations). Nitin Borkar has collaborated with scholars based in United States, India and Sweden. Frequent co-authors include Yatin Hoskote, Sriram Vangal, Shekhar Borkar, Saurabh Dighe, Jason Howard, Shailendra Jain, James Tschanz, Tiju Jacob, Vasantha Erraguntla and Greg Ruhl. Their work appears in journals such as SHILAP Revista de lepidopterología, IEEE Journal of Solid-State Circuits and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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