Nitin Borkar

5.0k total citations · 5 hit papers
37 papers, 3.1k citations indexed

About

Nitin Borkar is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Hardware and Architecture. According to data from OpenAlex, Nitin Borkar has authored 37 papers receiving a total of 3.1k indexed citations (citations by other indexed papers that have themselves been cited), including 29 papers in Electrical and Electronic Engineering, 17 papers in Computer Networks and Communications and 16 papers in Hardware and Architecture. Recurrent topics in Nitin Borkar's work include Low-power high-performance VLSI design (23 papers), Interconnection Networks and Systems (16 papers) and Parallel Computing and Optimization Techniques (11 papers). Nitin Borkar is often cited by papers focused on Low-power high-performance VLSI design (23 papers), Interconnection Networks and Systems (16 papers) and Parallel Computing and Optimization Techniques (11 papers). Nitin Borkar collaborates with scholars based in United States, India and Sweden. Nitin Borkar's co-authors include Yatin Hoskote, Sriram Vangal, Shekhar Borkar, Saurabh Dighe, Jason Howard, Shailendra Jain, James Tschanz, Tiju Jacob, Vasantha Erraguntla and Greg Ruhl and has published in prestigious journals such as SHILAP Revista de lepidopterología, IEEE Journal of Solid-State Circuits and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Nitin Borkar

36 papers receiving 2.9k citations

Hit Papers

5 papers align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

2007 474 citations Sriram Vangal, Jason Howard et al. profile →
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

2008 466 citations Sriram Vangal, Jason Howard et al. IEEE Journal of Solid-State Circuits profile →
A 5-GHz Mesh Interconnect for a Teraflops Processor

2007 416 citations Yatin Hoskote, Sriram Vangal et al. IEEE Micro profile →
A 5-GHz Mesh Interconnect for a Teraflops Processor

2007 415 citations Yatin Hoskote, Sriram Vangal et al. IEEE Micro profile →
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

2010 303 citations Jason Howard, Saurabh Dighe et al. IEEE Journal of Solid-State Circuits profile →

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Nitin Borkar United States	19	2.2k	1.9k	1.9k	351	134	37	3.1k
Yatin Hoskote United States	16	2.2k 1.0×	1.9k 1.0×	1.7k 0.9×	436 1.2×	97 0.7×	31	3.0k
A. Ivanov Canada	24	1.6k 0.7×	1.8k 0.9×	1.7k 0.9×	314 0.9×	207 1.5×	145	2.7k
Sriram Vangal United States	15	1.3k 0.6×	1.2k 0.6×	1.4k 0.7×	245 0.7×	131 1.0×	29	2.0k
Jason Howard United States	13	1.3k 0.6×	1.2k 0.6×	1.0k 0.5×	150 0.4×	58 0.4×	24	1.8k
Saurabh Dighe United States	10	1.2k 0.6×	1.2k 0.6×	1.0k 0.5×	150 0.4×	54 0.4×	13	1.7k
Victor Zyuban United States	22	1.1k 0.5×	1.6k 0.8×	1.5k 0.8×	78 0.2×	99 0.7×	49	2.3k
Amlan Ganguly United States	19	1.4k 0.7×	582 0.3×	1.0k 0.6×	262 0.7×	113 0.8×	74	1.7k
Karam S. Chatha United States	24	1.3k 0.6×	1.4k 0.7×	841 0.4×	136 0.4×	26 0.2×	75	1.7k
Vasantha Erraguntla United States	14	838 0.4×	834 0.4×	831 0.4×	99 0.3×	81 0.6×	20	1.3k
James Tschanz United States	34	1.3k 0.6×	2.1k 1.1×	4.4k 2.3×	144 0.4×	812 6.1×	146	5.1k

Countries citing papers authored by Nitin Borkar

Since Specialization

Citations

This map shows the geographic impact of Nitin Borkar's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Nitin Borkar with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Nitin Borkar more than expected).

Fields of papers citing papers by Nitin Borkar

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Nitin Borkar. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Nitin Borkar. The network helps show where Nitin Borkar may publish in the future.

Co-authorship network of co-authors of Nitin Borkar

This figure shows the co-authorship network connecting the top 25 collaborators of Nitin Borkar. A scholar is included among the top collaborators of Nitin Borkar based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Nitin Borkar. Nitin Borkar is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Borkar, Nitin, et al.. (2024). Immediate Hemodynamic Changes during Slow Uninostril and Alternate Nostril Breathing Patterns in Normotensive Adults. SHILAP Revista de lepidopterología. 17(3). 175–181.

Nair, Abhijit, et al.. (2023). Efficacy and safety of oral tizanidine premedication as pre-emptive analgesia in adult patients undergoing elective surgeries- A systematic review. Saudi Journal of Anaesthesia. 17(2). 214–222. 1 indexed citations

Nair, Abhijit, et al.. (2023). Ultrasound-guided transversalis fascia plane block for postoperative analgesia: A systematic review and meta-analysis. Indian Journal of Anaesthesia. 67(4). 331–342. 7 indexed citations

Park, Sang Phill, Dinesh Somasekhar, Young Moon Kim, et al.. (2016). System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24(12). 3468–3476. 11 indexed citations

Karnik, Tanay, James Tschanz, Nitin Borkar, et al.. (2014). Resiliency for many-core system on a chip. 388–389. 2 indexed citations

Dighe, Saurabh, Shailendra Jain, Satish Yada, et al.. (2012). An IA-32 processor with a wide voltage operating range in 32nm CMOS. 1–37. 1 indexed citations

Dighe, Saurabh, Sumeet Kumar Gupta, Vivek De, et al.. (2011). A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. 250–251. 12 indexed citations

Dighe, Saurabh, Sriram Vangal, Paolo Aseron, et al.. (2010). Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE Journal of Solid-State Circuits. 46(1). 184–193. 95 indexed citations

Khellah, Muhammad, Nam Sung Kim, Yibin Ye, et al.. (2009). Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE Journal of Solid-State Circuits. 44(4). 1199–1208. 17 indexed citations

10.

Vangal, Sriram, Jason Howard, Greg Ruhl, et al.. (2008). An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE Journal of Solid-State Circuits. 43(1). 29–41. 466 indexed citations breakdown →

11.

Hoskote, Yatin, et al.. (2007). A 5-GHz Mesh Interconnect for a Teraflops Processor. IEEE Micro. 27(5). 51–61. 415 indexed citations breakdown →

12.

Vangal, Sriram, Jason Howard, Saurabh Dighe, et al.. (2007). An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. 98–589. 474 indexed citations breakdown →

13.

Khellah, Muhammad, Dinesh Somasekhar, Nam Sung Kim, et al.. (2007). A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE Journal of Solid-State Circuits. 42(1). 233–242. 45 indexed citations

14.

Khellah, Muhammad, Nam Sung Kim, Jason Howard, et al.. (2006). A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS. 2572–2581. 23 indexed citations

15.

Vangal, Sriram, Yatin Hoskote, Nitin Borkar, & Atila Alvandpour. (2006). A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization. IEEE Journal of Solid-State Circuits. 41(10). 2314–2323. 49 indexed citations

16.

Borkar, Nitin, Erik Seligman, Vasantha Erraguntla, et al.. (2005). 5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 2. 334–535. 1 indexed citations

17.

Borkar, Nitin, et al.. (2005). A Six-Port 57GB/s Double-Pumped Nonblocking Router Core. 36. 268–269. 13 indexed citations

18.

Vangal, Sriram, Yatin Hoskote, Dinesh Somasekhar, et al.. (2003). A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS. 1. 334–497. 15 indexed citations

19.

Hoskote, Yatin, B. Bloechel, G. Dermer, et al.. (2003). A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS. IEEE Journal of Solid-State Circuits. 38(11). 1866–1875. 30 indexed citations

20.

Nair, R., et al.. (2002). A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes. 224–225,. 14 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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