Paolo Aseron

1.2k total citations
24 papers, 676 citations indexed

About

Paolo Aseron is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Paolo Aseron has authored 24 papers receiving a total of 676 indexed citations (citations by other indexed papers that have themselves been cited), including 22 papers in Electrical and Electronic Engineering, 11 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in Paolo Aseron's work include Low-power high-performance VLSI design (12 papers), Semiconductor materials and devices (9 papers) and VLSI and Analog Circuit Testing (6 papers). Paolo Aseron is often cited by papers focused on Low-power high-performance VLSI design (12 papers), Semiconductor materials and devices (9 papers) and VLSI and Analog Circuit Testing (6 papers). Paolo Aseron collaborates with scholars based in United States and India. Paolo Aseron's co-authors include Vivek De, James Tschanz, Keith Bowman, Tanay Karnik, Muhammad Khellah, Carlos Tokunaga, Arijit Raychowdhury, Bibiche Geuskens, Chris Wilkerson and Jason Howard and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

In The Last Decade

Paolo Aseron

19 papers receiving 657 citations

Peers

Paolo Aseron
M. Pearce United States
Joshua Friedrich United States
Ivan Miro-Panades France
Shih‐Lien L. Lu United States
Milovan Blagojević United States
S. Santhanam United States
Kaijian Shi United States
M.K. Gowan United States
J. Montanaro United States
G. Dermer United States
M. Pearce United States
Paolo Aseron
Citations per year, relative to Paolo Aseron Paolo Aseron (= 1×) peers M. Pearce

Countries citing papers authored by Paolo Aseron

Since Specialization
Citations

This map shows the geographic impact of Paolo Aseron's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Paolo Aseron with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Paolo Aseron more than expected).

Fields of papers citing papers by Paolo Aseron

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Paolo Aseron. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Paolo Aseron. The network helps show where Paolo Aseron may publish in the future.

Co-authorship network of co-authors of Paolo Aseron

This figure shows the co-authorship network connecting the top 25 collaborators of Paolo Aseron. A scholar is included among the top collaborators of Paolo Aseron based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Paolo Aseron. Paolo Aseron is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
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Srinivasa, Srivatsa, et al.. (2022). Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. 1–4. 5 indexed citations
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Paul, Somnath, Ryan Kim, Paolo Aseron, et al.. (2017). A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. IEEE Journal of Solid-State Circuits. 52(4). 961–971. 46 indexed citations
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Kulkarni, Jaydeep P., Carlos Tokunaga, Paolo Aseron, et al.. (2015). A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE Journal of Solid-State Circuits. 51(1). 117–129. 12 indexed citations
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Dighe, Saurabh, Shailendra Jain, Satish Yada, et al.. (2012). An IA-32 processor with a wide voltage operating range in 32nm CMOS. 1–37. 1 indexed citations
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Bowman, Keith, Carlos Tokunaga, James Tschanz, et al.. (2011). All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Transactions on Circuits and Systems I Regular Papers. 58(9). 2017–2025. 27 indexed citations
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Raychowdhury, Arijit, Jim Tschanz, Keith Bowman, et al.. (2011). Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 1(3). 208–217. 7 indexed citations
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Bowman, Keith, James Tschanz, Shih‐Lien L. Lu, et al.. (2010). Resilient microprocessor design for high performance & energy efficiency. 355–356.
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Bowman, Keith, James Tschanz, Shih‐Lien L. Lu, et al.. (2010). A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE Journal of Solid-State Circuits. 46(1). 194–208. 192 indexed citations
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Dighe, Saurabh, Sriram Vangal, Paolo Aseron, et al.. (2010). Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE Journal of Solid-State Circuits. 46(1). 184–193. 95 indexed citations
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Tschanz, James, Keith Bowman, Shih‐Lien Lu, et al.. (2010). A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. 282–283. 54 indexed citations
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Bowman, Keith, Carlos Tokunaga, James Tschanz, et al.. (2010). Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. 1–4. 28 indexed citations
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Xu, Jianping, P. Hazucha, Paolo Aseron, et al.. (2008). A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. IEEE Journal of Solid-State Circuits. 43(1). 61–68. 2 indexed citations
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Somasekhar, Dinesh, Yibin Ye, Paolo Aseron, et al.. (2008). 2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. 274–613. 20 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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