Steven Hsu

1.6k total citations
71 papers, 1.2k citations indexed

About

Steven Hsu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Artificial Intelligence. According to data from OpenAlex, Steven Hsu has authored 71 papers receiving a total of 1.2k indexed citations (citations by other indexed papers that have themselves been cited), including 53 papers in Electrical and Electronic Engineering, 27 papers in Hardware and Architecture and 17 papers in Artificial Intelligence. Recurrent topics in Steven Hsu's work include Low-power high-performance VLSI design (25 papers), Advancements in Semiconductor Devices and Circuit Design (22 papers) and Semiconductor materials and devices (21 papers). Steven Hsu is often cited by papers focused on Low-power high-performance VLSI design (25 papers), Advancements in Semiconductor Devices and Circuit Design (22 papers) and Semiconductor materials and devices (21 papers). Steven Hsu collaborates with scholars based in United States, Taiwan and Canada. Steven Hsu's co-authors include Ram Krishnamurthy, Mark Anders, Amit Agarwal, Shekhar Borkar, Himanshu Kaul, Sanu Mathew, Sudhir Satpathy, Kaushik Roy, Vikram Suresh and Farhana Sheikh and has published in prestigious journals such as Applied Physics Letters, IEEE Journal of Solid-State Circuits and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Steven Hsu

69 papers receiving 1.2k citations

Peers

Steven Hsu
Frank K. Gürkaynak Switzerland
Selçuk Köse United States
Nathaniel Pinckney United States
Farhana Sheikh United States
Hubert Kaeslin Switzerland
Brian Zimmer United States
Izzat El Hajj United States
Mauro Olivieri Italy
Amir Yazdanbakhsh United States
Jeffrey Draper United States
Frank K. Gürkaynak Switzerland
Steven Hsu
Citations per year, relative to Steven Hsu Steven Hsu (= 1×) peers Frank K. Gürkaynak

Countries citing papers authored by Steven Hsu

Since Specialization
Citations

This map shows the geographic impact of Steven Hsu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Steven Hsu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Steven Hsu more than expected).

Fields of papers citing papers by Steven Hsu

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Steven Hsu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Steven Hsu. The network helps show where Steven Hsu may publish in the future.

Co-authorship network of co-authors of Steven Hsu

This figure shows the co-authorship network connecting the top 25 collaborators of Steven Hsu. A scholar is included among the top collaborators of Steven Hsu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Steven Hsu. Steven Hsu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Kumar, Raghavan, Vikram Suresh, Sachin Taneja, et al.. (2022). A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 138–139. 2 indexed citations
2.
Vangal, Sriram, Somnath Paul, Steven Hsu, et al.. (2021). Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29(5). 843–856. 8 indexed citations
3.
Kumar, Raghavan, Vikram Suresh, Monodeep Kar, et al.. (2020). A 4900-$\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE Journal of Solid-State Circuits. 55(4). 945–955. 17 indexed citations
4.
Hsu, Steven, Amit Agarwal, Monodeep Kar, et al.. (2019). A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. C50–C51. 3 indexed citations
5.
6.
Suresh, Vikram, Sudhir Satpathy, Raghavan Kumar, et al.. (2019). A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. C32–C33. 5 indexed citations
7.
Kaul, Himanshu, Mark Anders, Sanu Mathew, et al.. (2018). Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. 1–4. 4 indexed citations
8.
Satpathy, Sudhir, Sanu Mathew, Vikram Suresh, et al.. (2018). 34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. 90–93. 8 indexed citations
9.
Suresh, Vikram, Sudhir Satpathy, Sanu Mathew, et al.. (2018). A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. 98–101. 4 indexed citations
10.
11.
Hsu, Steven, Chih-Wei Yang, Chien-Ting Lin, et al.. (2016). A New Figure of Merit, ${\Delta V_{\text {DIBLSS}} /(I_{\rm {d},{\mathrm{ sat}}} /I_{\rm {sd},{\mathrm{ leak}}} )}$ , to Characterize Short-Channel Performance of a Bulk-Si n-Channel FinFET Device. IEEE Journal of the Electron Devices Society. 5(1). 18–22. 6 indexed citations
12.
Mathew, Sanu, Sudhir Satpathy, Vikram Suresh, et al.. (2015). 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE Journal of Solid-State Circuits. 50(4). 1048–1058. 106 indexed citations
13.
14.
Agarwal, Amit, Steven Hsu, Sanu Mathew, et al.. (2011). A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. 83–86. 28 indexed citations
15.
16.
Kaul, Himanshu, Mark Anders, Sanu Mathew, et al.. (2008). A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. 316–616. 31 indexed citations
17.
Anders, Mark, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, & Shekhar Borkar. (2007). A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 9Onm CMOS. 256–600. 2 indexed citations
18.
Mathew, Sanu, David Harris, Mark Anders, Steven Hsu, & Ram Krishnamurthy. (2007). A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS. 25–28. 1 indexed citations
19.
Kim, C.H., Kaushik Roy, Steven Hsu, et al.. (2004). A process variation compensating technique for sub-90 nm dynamic circuits. 205–206. 34 indexed citations
20.
Hsu, Steven, et al.. (2002). Dynamic addressing memory arrays with physical locality. 161–170. 3 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

Breakdown of academic impact, for papers by Frank K. Gürkaynak Breakdown of academic impact, for papers by Selçuk Köse Breakdown of academic impact, for papers by Nathaniel Pinckney Breakdown of academic impact, for papers by Farhana Sheikh Breakdown of academic impact, for papers by Hubert Kaeslin Breakdown of academic impact, for papers by Brian Zimmer Breakdown of academic impact, for papers by Izzat El Hajj Breakdown of academic impact, for papers by Mauro Olivieri Breakdown of academic impact, for papers by Amir Yazdanbakhsh Breakdown of academic impact, for papers by Jeffrey Draper
Rankless by CCL
2026