Sanu Mathew

3.6k citations

127 papers · 2.7k indexed · h-index 30

Impact in

Hardware and Architecture top 0.2%
- Physical Unclonable Functions (PUFs) and Hardware Security
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 2%
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design

Papers in

Hardware and Architecture 73
- Physical Unclonable Functions (PUFs) and Hardware Security 43
Artificial Intelligence 53
- Cryptographic Implementations and Security 41
- Security and Verification in Computing 14

Co-authors: Ram Krishnamurthy Mark Anders Himanshu Kaul Amit Agarwal Vivek De Shekhar Borkar Sudhir Satpathy Steven K. Hsu
Journals: IEEE Journal of Solid-State Circuits (28 papers)IEEE Solid-State Circuits Letters (3 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1 paper)IEEE Transactions on Power Electronics (1 paper)Indian Journal of Science and Technology (1 paper)
Partner nations: United States India Israel

In The Last Decade

Sanu Mathew

120 papers receiving 2.6k citations

Peers

Countries citing papers authored by Sanu Mathew

Since Specialization

Citations

This map shows the geographic impact of Sanu Mathew's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sanu Mathew with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sanu Mathew more than expected).

Fields of papers citing papers by Sanu Mathew

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sanu Mathew. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sanu Mathew. The network helps show where Sanu Mathew may publish in the future.

Co-authors

The 25 scholars most cited alongside Sanu Mathew, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Sanu Mathew Line = papers co-authored together Sanu Mathew links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS IEEE Journal of Solid-State Circuits ·Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew	2025	0
2	GUARD: A Fully-Digital TDC-Based Clock and Voltage Glitch Detector with On-Demand Protection in a 28nm CMOS Mao Li, Paul Xuanyuanliang Huang, Jaehan Park, Sanu Mathew, Vivek De, Mingoo Seok	2025	0
3	A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor IEEE Solid-State Circuits Letters ·S. KONNO, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash L. Varna, Sanu Mathew, Arijit Raychowdhury	2025	0
4	A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω S. KONNO, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash L. Varna, Sanu Mathew, Arijit Raychowdhury	2024	1
5	UFC: A Unified Accelerator for Fully Homomorphic Encryption Minxuan Zhou, Yujin Nam, Xuan Wang, Y.-W. Lee, Chris Wilkerson, Raghavan Kumar, Sachin Taneja, Sanu Mathew, Rosario Cammarota, Tajana Rosing	2024	1
6	A Fully-Digital Variation-Tolerant Runtime Detector for PCB-Level Probing Attack in a 28-nm CMOS IEEE Solid-State Circuits Letters ·Mao Li, Yunze Yang, Weifeng He, Sanu Mathew, Vivek De, Mingoo Seok	2023	3
7	EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Debayan Das, Mayukh Nath, Baibhab Chatterjee, Raghavan Kumar, Xiaosen Liu, Harish K. Krishnamurthy, Manoj Sastry, Sanu Mathew, Santosh Ghosh, Shreyas Sen	2022	5
8	A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS IEEE Journal of Solid-State Circuits ·Raghavan Kumar, Xiaosen Liu, Vikram Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew	2021	18
9	EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing IEEE Journal of Solid-State Circuits ·Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong‐Hyun Seo, Muya Chang, Avinash L. Varna, Harish K. Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen	2020	36
10	Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators Himanshu Kaul, Mark Anders, Sanu Mathew, Seongjong Kim, Ram Krishnamurthy	2019	13
11	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS Steven Hsu, Amit Agarwal, Monodeep Kar, Mark Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De	2019	3
12	A 4900×m² 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition Raghavan Kumar, Vikram Suresh, Monodeep Kar, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew	2019	2
13	Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS Himanshu Kaul, Mark Anders, Sanu Mathew, Vikram Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy	2018	4
14	340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS IEEE Journal of Solid-State Circuits ·Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory Chen, Ram Krishnamurthy	2015	106
15	16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS Sanu Mathew, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram Krishnamurthy, Vivek De	2014	192
16	340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2<sup>4</sup>)<sup>2</sup> polynomials in 22nm tri-gate CMOS Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, Mark Anders, Greg Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy	2014	9
17	A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS IEEE Journal of Solid-State Circuits ·Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar	2012	16
18	2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS Suresh Srinivasan, Sanu Mathew, R. Ramanarayanan, Farhana Sheikh, Mark Anders, Himanshu Kaul, Vasantha Erraguntla, Ram Krishnamurthy, G. Taylor	2010	46
19	A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores R. Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron	2008	3
20	A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS Sriram Vangal, Yatin Hoskote, Dinesh Somasekhar, Vasantha Erraguntla, Jason Howard, Greg Ruhl, V. Veeramachaneni, D. Finan, Sanu Mathew, Nitin Borkar	2003	15

About Sanu Mathew

Sanu Mathew is a scholar working on Hardware and Architecture, Artificial Intelligence, Electrical and Electronic Engineering, Computer Vision and Pattern Recognition and Computational Theory and Mathematics, having authored 127 papers that have together received 2.7k indexed citations. Recurring topics across this work include Physical Unclonable Functions (PUFs) and Hardware Security (43 papers), Low-power high-performance VLSI design (41 papers), Cryptographic Implementations and Security (41 papers), Chaos-based Image/Signal Encryption (18 papers), Semiconductor materials and devices (17 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers), Advanced Memory and Neural Computing (15 papers) and Security and Verification in Computing (14 papers). The work is most often cited by research in Hardware and Architecture (1.5k citations), Electrical and Electronic Engineering (1.7k citations), Artificial Intelligence (894 citations), Computer Vision and Pattern Recognition (534 citations) and Computational Theory and Mathematics (347 citations). Sanu Mathew has collaborated with scholars based in United States, India and Israel. Frequent co-authors include Ram Krishnamurthy, Mark Anders, Himanshu Kaul, Amit Agarwal, Vivek De, Shekhar Borkar, Sudhir Satpathy, Steven K. Hsu, Steven Hsu and Vikram Suresh. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Solid-State Circuits Letters, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Power Electronics and Indian Journal of Science and Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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