Sudhir Satpathy

1.7k citations

51 papers · 1.4k indexed · h-index 18

Hardware and Architecture top 0.5%
Electrical and Electronic Engineering top 5%
Computer Networks and Communications top 5%
Computer Vision and Pattern Recognition top 5%
Artificial Intelligence top 5%

Co-authors: Sanu Mathew Ram Krishnamurthy Mark Anders Himanshu Kaul Amit Agarwal Steven K. Hsu Ronald Dreslinski Vikram Suresh
Topics: Interconnection Networks and Systems (15 papers)Advanced Memory and Neural Computing (14 papers)Physical Unclonable Functions (PUFs) and Hardware Security (14 papers)
Cited by: Hardware and Architecture Computer Networks and Communications Electrical and Electronic Engineering
Journals: Communications of the ACM IEEE Journal of Solid-State Circuits Electronics Letters
Partner nations: United States India United Kingdom

In The Last Decade

Sudhir Satpathy

50 papers receiving 1.3k citations

Peers

Countries citing papers authored by Sudhir Satpathy

Since Specialization

Citations

This map shows the geographic impact of Sudhir Satpathy's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sudhir Satpathy with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sudhir Satpathy more than expected).

Fields of papers citing papers by Sudhir Satpathy

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sudhir Satpathy. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sudhir Satpathy. The network helps show where Sudhir Satpathy may publish in the future.

Co-authorship network of co-authors of Sudhir Satpathy

This figure shows the co-authorship network connecting the top 25 collaborators of Sudhir Satpathy. A scholar is included among the top collaborators of Sudhir Satpathy based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Sudhir Satpathy. Sudhir Satpathy is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Enhanced phase extraction in optical coherence elastography using discrete cosine transform for localized tissue characterization 2025 ·Laser Physics ·Sudhir Satpathy,Raju Poddar	0
2	A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS 2021 ·IEEE Journal of Solid-State Circuits ·Raghavan Kumar,Xiaosen Liu,Vikram Suresh,Harish K. Krishnamurthy,Sudhir Satpathy,Mark Anders,Himanshu Kaul,Krishnan Ravichandran,Vivek De,Sanu Mathew	18
3	A 4900-$\mu$ m² 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition 2020 ·IEEE Journal of Solid-State Circuits ·Raghavan Kumar,Vikram Suresh,Monodeep Kar,Sudhir Satpathy,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Gregory K. Chen,Ram Krishnamurthy,Vivek De,Sanu Mathew	17
4	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS 2019 ·Steven Hsu,Amit Agarwal,Monodeep Kar,Mark Anders,Himanshu Kaul,Raghavan Kumar,Sudhir Satpathy,Vikram Suresh,Sanu Mathew,Ram Krishnamurthy,Vivek De	3
5	A 4900×m² 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition 2019 ·Raghavan Kumar,Vikram Suresh,Monodeep Kar,Sudhir Satpathy,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Gregory Chen,Ram Krishnamurthy,Vivek De,Sanu Mathew	2
6	A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking 2019 ·Vikram Suresh,Sudhir Satpathy,Raghavan Kumar,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Ram Krishnamurthy,Vivek De,Sanu Mathew	5
7	Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS 2018 ·Himanshu Kaul,Mark Anders,Sanu Mathew,Vikram Suresh,Sudhir Satpathy,Amit Agarwal,Steven Hsu,Ram Krishnamurthy	4
8	34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms 2018 ·Sudhir Satpathy,Sanu Mathew,Vikram Suresh,(unknown),(unknown),Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,(unknown)	8
9	A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS 2018 ·Vikram Suresh,Sudhir Satpathy,Sanu Mathew,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Ram Krishnamurthy	4
10	An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms 2018 ·Sudhir Satpathy,Sanu Mathew,Vikram Suresh,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Ram Krishnamurthy,Vivek De	14
11	340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS 2015 ·IEEE Journal of Solid-State Circuits ·Sanu Mathew,Sudhir Satpathy,Vikram Suresh,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Gregory Chen,Ram Krishnamurthy	106
12	16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS 2014 ·Sanu Mathew,Sudhir Satpathy,Mark Anders,Himanshu Kaul,Steven K. Hsu,Amit Agarwal,Gregory K. Chen,Rachael J. Parker,Ram Krishnamurthy,Vivek De	192
13	340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2<sup>4</sup>)<sup>2</sup> polynomials in 22nm tri-gate CMOS 2014 ·Sanu Mathew,Sudhir Satpathy,Vikram Suresh,Himanshu Kaul,Mark Anders,(unknown),Amit Agarwal,Steven Hsu,Ram Krishnamurthy	9
14	Centip3De: A 64-Core, 3D Stacked Near-Threshold System 2013 ·IEEE Micro ·Ronald Dreslinski,David Fick,Bharan Giridhar,Gyouho Kim,Sangwon Seo,Matthew Fojtik,Sudhir Satpathy,Yoonmyung Lee,(unknown),Nurrachman Liu,Michael Wieckowski,Gregory Chen,Dennis Sylvester,David Blaauw,Trevor Mudge	29
15	Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS 2012 ·IEEE Journal of Solid-State Circuits ·David Fick,Ronald Dreslinski,Bharan Giridhar,Gyouho Kim,Sangwon Seo,Matthew Fojtik,Sudhir Satpathy,Yoonmyung Lee,Daeyeon Kim,Nurrachman Liu,Michael Wieckowski,Gregory Chen,Trevor Mudge,David Blaauw,Dennis Sylvester	27
16	High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service 2012 ·Sudhir Satpathy,Reetuparna Das,Ronald Dreslinski,Trevor Mudge,Dennis Sylvester,David Blaauw	2
17	A standard cell compatible bidirectional repeater with thyristor assist 2012 ·Sudhir Satpathy,Dennis Sylvester,David Blaauw	1
18	A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS 2012 ·Sudhir Satpathy,Korey Sewell,(unknown),Yen‐Po Chen,Ronald Dreslinski,Dennis Sylvester,Trevor Mudge,David Blaauw	16
19	Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems 2012 ·Ronald Dreslinski,Korey Sewell,(unknown),Sudhir Satpathy,Nathaniel Pinckney,(unknown),(unknown),Reetuparna Das,Thomas F. Wenisch,Dennis Sylvester,David Blaauw,Trevor Mudge	4
20	Centip3De: A 64-core, 3D stacked, near-threshold system 2012 ·Ronald Dreslinski,David Fick,Bharan Giridhar,Gyouho Kim,Sangwon Seo,Matthew Fojtik,Sudhir Satpathy,Yoonmyung Lee,(unknown),Nurrachman Liu,Michael Wieckowski,Gregory Chen,Trevor Mudge,Dennis Sylvester,David Blaauw	3

About Sudhir Satpathy

Sudhir Satpathy is a scholar working on Hardware and Architecture, Computer Networks and Communications and Computational Theory and Mathematics, having authored 51 papers that have together received 1.4k indexed citations. Recurring topics across this work include Interconnection Networks and Systems (15 papers), Advanced Memory and Neural Computing (14 papers) and Physical Unclonable Functions (PUFs) and Hardware Security (14 papers). The work is most often cited by research in Hardware and Architecture (937 citations), Computer Networks and Communications (389 citations) and Electrical and Electronic Engineering (906 citations). Sudhir Satpathy has collaborated with scholars based in United States, India and United Kingdom. Frequent co-authors include Sanu Mathew, Ram Krishnamurthy, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven K. Hsu, Ronald Dreslinski, Vikram Suresh, Vivek De and Gregory Chen. Their work appears in journals such as Communications of the ACM, IEEE Journal of Solid-State Circuits and Electronics Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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