Himanshu Kaul

2.6k total citations
84 papers, 2.0k citations indexed

About

Himanshu Kaul is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Artificial Intelligence. According to data from OpenAlex, Himanshu Kaul has authored 84 papers receiving a total of 2.0k indexed citations (citations by other indexed papers that have themselves been cited), including 61 papers in Electrical and Electronic Engineering, 43 papers in Hardware and Architecture and 21 papers in Artificial Intelligence. Recurrent topics in Himanshu Kaul's work include Low-power high-performance VLSI design (33 papers), Parallel Computing and Optimization Techniques (16 papers) and Physical Unclonable Functions (PUFs) and Hardware Security (15 papers). Himanshu Kaul is often cited by papers focused on Low-power high-performance VLSI design (33 papers), Parallel Computing and Optimization Techniques (16 papers) and Physical Unclonable Functions (PUFs) and Hardware Security (15 papers). Himanshu Kaul collaborates with scholars based in United States, United Kingdom and India. Himanshu Kaul's co-authors include Mark Anders, Ram Krishnamurthy, Sanu Mathew, Amit Agarwal, Steven K. Hsu, Sudhir Satpathy, Steven Hsu, Dennis Sylvester, Shekhar Borkar and Farhana Sheikh and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Solid-State Circuits Letters.

In The Last Decade

Himanshu Kaul

84 papers receiving 2.0k citations

Peers

Himanshu Kaul
Amit Agarwal United States
Sanu Mathew United States
Swaroop Ghosh United States
Swagath Venkataramani United States
Sudhir Satpathy United States
Ram Krishnamurthy United States
Gi-Joon Nam United States
Georg Sigl Germany
Ren-Shuo Liu Taiwan
Yuan Cao China
Amit Agarwal United States
Himanshu Kaul
Citations per year, relative to Himanshu Kaul Himanshu Kaul (= 1×) peers Amit Agarwal

Countries citing papers authored by Himanshu Kaul

Since Specialization
Citations

This map shows the geographic impact of Himanshu Kaul's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Himanshu Kaul with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Himanshu Kaul more than expected).

Fields of papers citing papers by Himanshu Kaul

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Himanshu Kaul. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Himanshu Kaul. The network helps show where Himanshu Kaul may publish in the future.

Co-authorship network of co-authors of Himanshu Kaul

This figure shows the co-authorship network connecting the top 25 collaborators of Himanshu Kaul. A scholar is included among the top collaborators of Himanshu Kaul based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Himanshu Kaul. Himanshu Kaul is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Kumar, Raghavan, Xiaosen Liu, Vikram Suresh, et al.. (2021). A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. IEEE Journal of Solid-State Circuits. 56(4). 1141–1151. 18 indexed citations
2.
Kumar, Raghavan, Vikram Suresh, Monodeep Kar, et al.. (2020). A 4900-$\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE Journal of Solid-State Circuits. 55(4). 945–955. 17 indexed citations
3.
Kaul, Himanshu, Mark Anders, Sanu Mathew, Seongjong Kim, & Ram Krishnamurthy. (2019). Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators. 84–87. 13 indexed citations
4.
Hsu, Steven, Amit Agarwal, Monodeep Kar, et al.. (2019). A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. C50–C51. 3 indexed citations
5.
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7.
Kaul, Himanshu, Mark Anders, Sanu Mathew, et al.. (2018). Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. 1–4. 4 indexed citations
8.
Satpathy, Sudhir, Sanu Mathew, Vikram Suresh, et al.. (2018). 34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. 90–93. 8 indexed citations
9.
Suresh, Vikram, Sudhir Satpathy, Sanu Mathew, et al.. (2018). A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. 98–101. 4 indexed citations
10.
Mathew, Sanu, Sudhir Satpathy, Vikram Suresh, et al.. (2015). 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE Journal of Solid-State Circuits. 50(4). 1048–1058. 106 indexed citations
11.
Mathew, Sanu, Sudhir Satpathy, Mark Anders, et al.. (2014). 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. 278–279. 192 indexed citations
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Sheikh, Farhana, Sanu Mathew, Mark Anders, et al.. (2012). A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE Journal of Solid-State Circuits. 48(1). 128–139. 16 indexed citations
14.
Srinivasan, Suresh, Sanu Mathew, R. Ramanarayanan, et al.. (2010). 2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS. 203–204. 46 indexed citations
15.
Kaul, Himanshu, Mark Anders, Sanu Mathew, et al.. (2010). A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE Journal of Solid-State Circuits. 45(1). 95–102. 32 indexed citations
16.
Kaul, Himanshu, Mark Anders, Sanu Mathew, et al.. (2009). A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE Journal of Solid-State Circuits. 44(1). 107–114. 60 indexed citations
17.
Kaul, Himanshu, Mark Anders, Sanu Mathew, et al.. (2008). A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. 316–616. 31 indexed citations
18.
Kaul, Himanshu & Dennis Sylvester. (2005). A novel buffer circuit for energy efficient signaling in dual-VDD systems. 28. 462–467. 9 indexed citations
19.
Sylvester, Dennis, Himanshu Kaul, Kanak Agarwal, et al.. (2005). Power-Aware Global Signaling Strategies. 9. 604–607. 1 indexed citations
20.
Kaul, Himanshu & Dennis Sylvester. (2003). Transition aware global signaling (TAGS). 53–59. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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