Soner Yaldiz

480 total citations
28 papers, 369 citations indexed

About

Soner Yaldiz is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Soner Yaldiz has authored 28 papers receiving a total of 369 indexed citations (citations by other indexed papers that have themselves been cited), including 26 papers in Electrical and Electronic Engineering, 14 papers in Hardware and Architecture and 4 papers in Biomedical Engineering. Recurrent topics in Soner Yaldiz's work include VLSI and Analog Circuit Testing (11 papers), Low-power high-performance VLSI design (10 papers) and Radio Frequency Integrated Circuit Design (9 papers). Soner Yaldiz is often cited by papers focused on VLSI and Analog Circuit Testing (11 papers), Low-power high-performance VLSI design (10 papers) and Radio Frequency Integrated Circuit Design (9 papers). Soner Yaldiz collaborates with scholars based in United States, China and Türkiye. Soner Yaldiz's co-authors include Xin Li, Larry Pileggi, Arun Natarajan, Mark Ferriss, Alberto Valdes‐Garcia, Daniel J. Friedman, Matthias Althoff, Akshay Rajhans, Bodhisatwa Sadhu and Ramesh Harjani and has published in prestigious journals such as Communications of the ACM, IEEE Journal of Solid-State Circuits and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Soner Yaldiz

27 papers receiving 360 citations

Peers

Countries citing papers authored by Soner Yaldiz

Since Specialization

Citations

This map shows the geographic impact of Soner Yaldiz's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Soner Yaldiz with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Soner Yaldiz more than expected).

Fields of papers citing papers by Soner Yaldiz

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Soner Yaldiz. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Soner Yaldiz. The network helps show where Soner Yaldiz may publish in the future.

Co-authorship network of co-authors of Soner Yaldiz

This figure shows the co-authorship network connecting the top 25 collaborators of Soner Yaldiz. A scholar is included among the top collaborators of Soner Yaldiz based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Soner Yaldiz. Soner Yaldiz is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients 2024 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Arvind Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, (unknown), Ramesh Harjani, Sachin S. Sapatnekar	1
2	A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework 2023 ·IEEE Solid-State Circuits Letters ·Xiaosen Liu, Soner Yaldiz, (unknown), Steven M. Burns, Harish K. Krishnamurthy, Krishnan Ravichandran, (unknown), Nachiket Desai, Nicolas Butzen, James Tschanz, Vivek De	2
3	A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts 2023 ·ACM Transactions on Design Automation of Electronic Systems ·(unknown), Meghna Madhusudan, Arvind Sharma, (unknown), Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar	5
4	A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework 2022 ·Xiaosen Liu, Soner Yaldiz, (unknown), Steven M. Burns, Harish K. Krishnamurthy, Krishnan Ravichandran, (unknown), Nachiket Desai, Nicolas Butzen, James Tschanz, Vivek De	6
5	Analog/Mixed-Signal Layout Optimization using Optimal Well Taps 2022 ·(unknown), Meghna Madhusudan, Arvind Sharma, (unknown), Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar	4
6	Common-Centroid Layouts for Analog Circuits: Advantages and Limitations 2021 ·Arvind Sharma, Meghna Madhusudan, Steven M. Burns, (unknown), Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar	20
7	Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits 2021 ·Arvind Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, (unknown), Ramesh Harjani, Sachin S. Sapatnekar	12
8	The ALIGN open-source analog layout generator 2020 ·(unknown), Kishor Kunal, (unknown), (unknown), Meghna Madhusudan, (unknown), Arvind Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, (unknown), Soner Yaldiz, Sachin S. Sapatnekar	4
9	A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology 2015 ·(unknown), (unknown), (unknown), Soner Yaldiz, (unknown), Nasser Kurd	11
10	Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion 2013 ·(unknown), (unknown), Soner Yaldiz, (unknown), Larry Pileggi, Arun Natarajan, Mark Ferriss, Jean‐Olivier Plouchart, Bodhisatwa Sadhu, B. Parker, Alberto Valdes‐Garcia, Mihai Sanduleanu, J. Tierno, Daniel J. Friedman	17
11	A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS 2013 ·IEEE Transactions on Circuits and Systems I Regular Papers ·Jean‐Olivier Plouchart, Mark Ferriss, Arun Natarajan, Alberto Valdes‐Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, B. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott Reynolds, J. Tierno, Daniel J. Friedman	14
12	Formal verification of phase-locked loops using reachability analysis and continuization 2013 ·Communications of the ACM ·Matthias Althoff, Akshay Rajhans, Bruce H. Krogh, Soner Yaldiz, Xin Li, Larry Pileggi	19
13	An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS 2012 ·Mark Ferriss, Jean‐Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes‐Garcia, José Tierno, Daniel J. Friedman	5
14	A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier 2012 ·Bodhisatwa Sadhu, Mark Ferriss, Jean‐Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Alberto Valdes‐Garcia, Benjamin D. Parker, Scott Reynolds, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, José Tierno, Daniel J. Friedman	6
15	Formal verification of phase-locked loops using reachability analysis and continuization 2011 ·International Conference on Computer Aided Design ·Matthias Althoff, Akshay Rajhans, Bruce H. Krogh, Soner Yaldiz, Xin Li, Larry Pileggi	26
16	Indirect phase noise sensing for self-healing voltage controlled oscillators 2011 ·Soner Yaldiz, (unknown), (unknown), Larry Pileggi, Arun Natarajan, Mark Ferriss, J. Tierno	10
17	Efficient statistical analysis of read timing failures in SRAM circuits 2009 ·Soner Yaldiz, Ümüt Arslan, Xin Li, Larry Pileggi	9
18	Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study 2008 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Soner Yaldiz, Alper Demir, Serdar Taşiran	6
19	Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management 2005 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Soner Yaldiz, (unknown), Serdar Taşiran, Paolo Ienne, Yusuf Leblebici	3
20	Characterizing and exploiting task load variability and correlation for energy management in multi core systems 2005 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Soner Yaldiz, Alper Demir, Serdar Taşiran, Paolo Ienne, Yusuf Leblebici	6

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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