Subhasish Mitra

18.1k total citations · 4 hit papers
353 papers, 13.2k citations indexed

About

Subhasish Mitra is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Materials Chemistry. According to data from OpenAlex, Subhasish Mitra has authored 353 papers receiving a total of 13.2k indexed citations (citations by other indexed papers that have themselves been cited), including 310 papers in Electrical and Electronic Engineering, 138 papers in Hardware and Architecture and 70 papers in Materials Chemistry. Recurrent topics in Subhasish Mitra's work include Radiation Effects in Electronics (119 papers), VLSI and Analog Circuit Testing (108 papers) and Semiconductor materials and devices (97 papers). Subhasish Mitra is often cited by papers focused on Radiation Effects in Electronics (119 papers), VLSI and Analog Circuit Testing (108 papers) and Semiconductor materials and devices (97 papers). Subhasish Mitra collaborates with scholars based in United States, Taiwan and United Kingdom. Subhasish Mitra's co-authors include H.‐S. Philip Wong, Nishant Patil, E.J. McCluskey, Max M. Shulaker, Gage Hills, Hai Wei, N. Seifert, Kee Sup Kim, Hongyu Chen and Tony F. Wu and has published in prestigious journals such as Nature, Advanced Materials and Nano Letters.

In The Last Decade

Subhasish Mitra

337 papers receiving 12.7k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Carbon nanotube computer

2013 763 citations Max M. Shulaker, Gage Hills et al. profile →
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

2017 636 citations Max M. Shulaker, Gage Hills et al. profile →
Robust system design with built-in soft-error resilience

2005 409 citations Subhasish Mitra et al. profile →
The case for RAMClouds

2010 334 citations Subhasish Mitra et al. profile →

Peers

Countries citing papers authored by Subhasish Mitra

Since Specialization

Citations

This map shows the geographic impact of Subhasish Mitra's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Subhasish Mitra with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Subhasish Mitra more than expected).

Fields of papers citing papers by Subhasish Mitra

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Subhasish Mitra. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Subhasish Mitra. The network helps show where Subhasish Mitra may publish in the future.

Co-authorship network of co-authors of Subhasish Mitra

This figure shows the co-authorship network connecting the top 25 collaborators of Subhasish Mitra. A scholar is included among the top collaborators of Subhasish Mitra based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Subhasish Mitra. Subhasish Mitra is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Silent Data Corruption by 10× Test Escapes Threatens Reliable Computing 2025 ·IEEE Design and Test ·Subhasish Mitra, Subho S. Banerjee, Martin Dixon, Mike Fuller, Rama Govindaraju, Peter Hochschild, (unknown), (unknown), Parthasarathy Ranganathan	0
2	MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating 2024 ·(unknown), Robert M. Radway, (unknown), (unknown), Massimo Giordano, (unknown), (unknown), Win-San Khwa, Yu-Der Chih, Meng‐Fan Chang, Subhasish Mitra, Priyanka Raina	3
3	Hybrid 2T nMOS/pMOS Gain Cell Memory With Indium-Tin-Oxide and Carbon Nanotube MOSFETs for Counteracting Capacitive Coupling 2023 ·IEEE Electron Device Letters ·Shuhan Liu, Shengman Li, Qing Lin, (unknown), Subhasish Mitra, H.‐S. Philip Wong, Kasidit Toprasertpong	3
4	Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors 2023 ·ACS Nano ·Qing Lin, (unknown), Sheng‐Kai Su, Zichen Zhang, Edward Chen, Prabhakar R. Bandaru, Andrew C. Kummel, Iuliana Radu, Subhasish Mitra, Gregory Pitner, H.‐S. Philip Wong	11
5	Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors 2022 ·IEEE Transactions on Electron Devices ·(unknown), (unknown), Youngki Yoon, Eric Pop, H.‐S. Philip Wong, Subhasish Mitra	12
6	Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs 2022 ·IEEE Electron Device Letters ·Qing Lin, Gregory Pitner, (unknown), Sheng‐Kai Su, Zichen Zhang, Edward Chen, Prabhakar R. Bandaru, Andrew C. Kummel, Han Wang, M. Passlack, Subhasish Mitra, H.‐S. Philip Wong	13
7	Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array 2021 ·IEEE Electron Device Letters ·E. R. Hsieh, Xin Zheng, Binh Le, Yi-Chun Shih, Robert M. Radway, Matthew D. Nelson, Subhasish Mitra, S.S. Wong	24
8	A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors 2020 ·(unknown), (unknown), (unknown), Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz	21
9	Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length 2020 ·Gregory Pitner, Zichen Zhang, Qing Lin, Sheng‐Kai Su, (unknown), (unknown), (unknown), T. Weiß, Zhouchangwan Yu, (unknown), Lain‐Jong Li, Subhasish Mitra, H.‐S. Philip Wong, J. Cai, Andrew C. Kummel, Prabhakar R. Bandaru, M. Passlack	27
10	Monolithic 3-D Integration 2019 ·IEEE Micro ·Mindy D. Bishop, H.‐S. Philip Wong, Subhasish Mitra, Max M. Shulaker	44
11	Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study 2018 ·Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Jan M. Rabaey, H.‐S. Philip Wong, Max M. Shulaker, Subhasish Mitra	104
12	Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration 2018 ·IEEE Journal of Solid-State Circuits ·Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Gage Hills, (unknown), (unknown), Jan M. Rabaey, H.‐S. Philip Wong, Max M. Shulaker, Subhasish Mitra	57
13	The N3XT Approach to Energy-Efficient Abundant-Data Computing 2018 ·Proceedings of the IEEE ·Mohamed M. Sabry Aly, Tony F. Wu, (unknown), (unknown), (unknown), Gage Hills, Igor L. Markov, Mary Wootters, Max M. Shulaker, H.‐S. Philip Wong, Subhasish Mitra	87
14	Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition 2016 ·Haitong Li, Tony F. Wu, Abbas Rahimi, Kai‐Shin Li, (unknown), Chang-Hsien Lin, (unknown), Mohamed M. Sabry, Sukru Burc Eryilmaz, Joon Sohn, (unknown), Min‐Cheng Chen, Tsung‐Ta Wu, Jia‐Min Shieh, Wen‐Kuan Yeh, Jan M. Rabaey, Subhasish Mitra, H.‐S. Philip Wong	110
15	Monolithic 3D integration: a path from concept to reality 2015 ·Design, Automation, and Test in Europe ·Max M. Shulaker, Tony F. Wu, Mohamed M. Sabry, Hai Wei, H.‐S. Philip Wong, Subhasish Mitra	21
16	Carbon nanotube imperfection-immune digital VLSI: frequently asked questions updated 2011 ·International Conference on Computer Aided Design ·Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hongyu Chen, H.‐S. Philip Wong, Subhasish Mitra	6
17	Architecture and performance evaluation of 3D CMOS-NEM FPGA 2011 ·Chen Dong, Chen Chen, Subhasish Mitra, Deming Chen	10
18	ERSA: error resilient system architecture for probabilistic applications 2010 ·Design, Automation, and Test in Europe ·Larkhoon Leem, Hyungmin Cho, (unknown), Quinn Jacobson, Subhasish Mitra	148
19	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links 2008 ·International Conference on Computer Aided Design ·Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	120
20	An output encoding problem and a solution technique 1997 ·International Conference on Computer Aided Design ·Subhasish Mitra, (unknown), E.J. McCluskey	1

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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