Raghavan Kumar

1.4k citations

62 papers · 887 indexed · h-index 16

Hardware and Architecture top 2%
- Physical Unclonable Functions (PUFs) and Hardware Security 29
Cellular and Molecular Neuroscience top 10%
- Neuroscience and Neural Engineering 9
Electrical and Electronic Engineering top 10%
- Advanced Memory and Neural Computing 19
- Integrated Circuits and Semiconductor Failure Analysis 11
- Low-power high-performance VLSI design 8
- Ferroelectric and Negative Capacitance Devices 5
Artificial Intelligence top 5%
- Cryptographic Implementations and Security 19
- Security and Verification in Computing 8
Computer Vision and Pattern Recognition top 10%

Co-authors: Wayne Burleson Ram Krishnamurthy H. Ekin Sumbul Phil Knag Gregory K. Chen Chan‐Hyun Sohn Sanu Mathew Sandip Kundu
Cited by: Hardware and Architecture Cellular and Molecular Neuroscience Electrical and Electronic Engineering
Journals: IEEE Journal of Solid-State Circuits (8 papers)IEEE Solid-State Circuits Letters (2 papers)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1 paper)
Partner nations: United States India Germany

In The Last Decade

Raghavan Kumar

59 papers receiving 871 citations

Peers

Countries citing papers authored by Raghavan Kumar

Since Specialization

Citations

This map shows the geographic impact of Raghavan Kumar's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Raghavan Kumar with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Raghavan Kumar more than expected).

Fields of papers citing papers by Raghavan Kumar

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Raghavan Kumar. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Raghavan Kumar. The network helps show where Raghavan Kumar may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Raghavan Kumar, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Raghavan Kumar Line = papers co-authored together Raghavan Kumar links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS IEEE Journal of Solid-State Circuits ·Raghavan Kumar,Sachin Taneja,Vivek De,Sanu Mathew	2025	0
2	UFC: A Unified Accelerator for Fully Homomorphic Encryption Minxuan Zhou,Yujin Nam,Xuan Wang,中島勝明,Chris Wilkerson,Raghavan Kumar,Sachin Taneja,Sanu Mathew,Rosario Cammarota,Tajana Rosing	2024	1
3	A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS Raghavan Kumar,Sachin Taneja,Vivek De,Sanu Mathew	2024	0
4	15.5 A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS Raghavan Kumar,Avinash L. Varna,Carlos Tokunaga,Sachin Taneja,Vivek De,Sanu Mathew	2023	9
5	Hardware-Software Co-design for Side-Channel Protected Neural Network Inference Simon J. James,Rosario Cammarota,Avinash L. Varna,Raghavan Kumar,Aydın Aysu	2023	4
6	EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Debayan Das,Mayukh Nath,Baibhab Chatterjee,Raghavan Kumar,Xiaosen Liu,Harish K. Krishnamurthy,Т А Фетисова,Sanu Mathew,Santosh Ghosh,Shreyas Sen	2022	5
7	A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Raghavan Kumar,Vikram Suresh,Sachin Taneja,Mark Anders,Steven Hsu,Amit Agarwal,Vivek De,Sanu Mathew	2022	2
8	A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS IEEE Journal of Solid-State Circuits ·Raghavan Kumar,Xiaosen Liu,Vikram Suresh,Harish K. Krishnamurthy,Sudhir Satpathy,Mark Anders,Himanshu Kaul,Krishnan Ravichandran,Vivek De,Sanu Mathew	2021	18
9	A 4900-$\mu$ m² 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition IEEE Journal of Solid-State Circuits ·Raghavan Kumar,Vikram Suresh,Monodeep Kar,Sudhir Satpathy,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Gregory K. Chen,Ram Krishnamurthy,Vivek De,Sanu Mathew	2020	17
10	Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs Eriko Nurvitadhi,Sabrina Barros Santiago,Ali Jafari,Andrew Boutros,Jaewoong Sim,Patrick Tonnius,H. Ekin Sumbul,Gregory Chen,Phil Knag,Raghavan Kumar,Ram Krishnamurthy,NIKITA A. SELIVERSTOV,Bogdan Pasca,Martin Langhammer,Debbie Marr,Aravind Dasu	2019	43
11	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS Steven Hsu,Amit Agarwal,Monodeep Kar,Mark Anders,Himanshu Kaul,Raghavan Kumar,Sudhir Satpathy,Vikram Suresh,Sanu Mathew,Ram Krishnamurthy,Vivek De	2019	3
12	A 4900×m² 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition Raghavan Kumar,Vikram Suresh,Monodeep Kar,Sudhir Satpathy,Mark Anders,Himanshu Kaul,Amit Agarwal,Steven Hsu,Gregory Chen,Ram Krishnamurthy,Vivek De,Sanu Mathew	2019	2
13	Physically Unclonable Functions: A Window into CMOS Process Variations Raghavan Kumar,Xiaolin Xu,Wayne Burleson,Sami Rosenblatt,T. Kirihata	2016	1
14	On design of a highly secure PUF based on non-linear current mirrors Raghavan Kumar,Wayne Burleson	2014	88
15	Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis Raghavan Kumar,Philipp Jovanovic,Ilia Polian	2014	12
16	Litho-aware and low power design of a secure current-based physically unclonable function Raghavan Kumar,Wayne Burleson	2013	3
17	Program phase duration prediction and its application to fine-grain power management Sudarshan Srinivasan,Raghavan Kumar,Sandip Kundu	2013	7
18	A high-speed cryogenic SiGe channel combiner IC for large photon-starved SNSPD arrays Joseph C. Bardin,Nancy Gerber,Su-Wei Chang,Raghavan Kumar,Jeffrey A. Stern,Matthew D. Shaw,Damon Russell,William H. Farr	2013	16
19	PHAP: Password based Hardware Authentication using PUFs Raghavan Kumar,Wayne Burleson	2012	3
20	On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators Raghavan Kumar,Daiji Hiarata,Sandip Kundu	2012	17

About Raghavan Kumar

Raghavan Kumar is a scholar working on Hardware and Architecture, Artificial Intelligence and Electrical and Electronic Engineering, having authored 62 papers that have together received 887 indexed citations. Recurring topics across this work include Physical Unclonable Functions (PUFs) and Hardware Security (29 papers), Advanced Memory and Neural Computing (19 papers), Cryptographic Implementations and Security (19 papers), Integrated Circuits and Semiconductor Failure Analysis (11 papers), Neuroscience and Neural Engineering (9 papers), Low-power high-performance VLSI design (8 papers), Security and Verification in Computing (8 papers) and Ferroelectric and Negative Capacitance Devices (5 papers). The work is most often cited by research in Hardware and Architecture (438 citations), Cellular and Molecular Neuroscience (187 citations) and Electrical and Electronic Engineering (572 citations). Raghavan Kumar has collaborated with scholars based in United States, India and Germany. Frequent co-authors include Wayne Burleson, Ram Krishnamurthy, H. Ekin Sumbul, Phil Knag, Gregory K. Chen, Chan‐Hyun Sohn, Sanu Mathew, Sandip Kundu, Mark Anders and Vivek De. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Solid-State Circuits Letters, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, International Journal of Automation and Control and Recent Patents on Mechanical Engineering.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact