Michael Orshansky

5.4k total citations · 2 hit papers
120 papers, 4.1k citations indexed

About

Michael Orshansky is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computational Theory and Mathematics. According to data from OpenAlex, Michael Orshansky has authored 120 papers receiving a total of 4.1k indexed citations (citations by other indexed papers that have themselves been cited), including 100 papers in Electrical and Electronic Engineering, 52 papers in Hardware and Architecture and 15 papers in Computational Theory and Mathematics. Recurrent topics in Michael Orshansky's work include Low-power high-performance VLSI design (57 papers), VLSI and FPGA Design Techniques (36 papers) and VLSI and Analog Circuit Testing (30 papers). Michael Orshansky is often cited by papers focused on Low-power high-performance VLSI design (57 papers), VLSI and FPGA Design Techniques (36 papers) and VLSI and Analog Circuit Testing (30 papers). Michael Orshansky collaborates with scholars based in United States, Italy and Canada. Michael Orshansky's co-authors include Jie Han, Kurt Keutzer, Andreas Gerstlauer, Bin Zhang, Chenming Hu, Dennis Sylvester, Takashi Satō, Yu Cao, Miao Jin and Wei‐Shen Wang and has published in prestigious journals such as Communications of the ACM, IEEE Journal of Solid-State Circuits and IEEE Transactions on Computers.

In The Last Decade

Michael Orshansky

119 papers receiving 3.9k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Approximate computing: An emerging paradigm for energy-efficient design

2013 772 citations Michael Orshansky et al. profile →
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

2002 398 citations Michael Orshansky, Chenming Hu et al. profile →

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Michael Orshansky United States	33	3.6k	2.0k	425	396	326	120	4.1k
Ali Afzali‐Kusha Iran	31	2.7k 0.7×	994 0.5×	686 1.6×	582 1.5×	229 0.7×	271	3.2k
Neil Weste Australia	15	2.7k 0.8×	1.1k 0.5×	379 0.9×	758 1.9×	269 0.8×	70	3.3k
André DeHon United States	34	2.6k 0.7×	2.2k 1.1×	1.5k 3.6×	470 1.2×	440 1.3×	149	4.1k
Ram Krishnamurthy United States	33	2.8k 0.8×	1.6k 0.8×	462 1.1×	449 1.1×	655 2.0×	170	3.6k
Amit Agarwal United States	26	2.0k 0.6×	1.5k 0.7×	518 1.2×	174 0.4×	335 1.0×	102	2.7k
Sani Nassif United States	42	5.2k 1.4×	2.5k 1.2×	460 1.1×	366 0.9×	121 0.4×	181	5.7k
Akash Kumar Germany	32	2.2k 0.6×	2.3k 1.1×	1.7k 3.9×	248 0.6×	432 1.3×	333	4.1k
Massimo Alioto Singapore	38	3.8k 1.1×	1.2k 0.6×	308 0.7×	1.4k 3.4×	582 1.8×	302	4.7k
Alex Yakovlev United Kingdom	27	2.5k 0.7×	2.2k 1.1×	1.2k 2.8×	401 1.0×	501 1.5×	498	4.3k
Larry Pileggi United States	27	2.0k 0.6×	1.0k 0.5×	338 0.8×	229 0.6×	161 0.5×	151	2.5k

Countries citing papers authored by Michael Orshansky

Since Specialization

Citations

This map shows the geographic impact of Michael Orshansky's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Michael Orshansky with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Michael Orshansky more than expected).

Fields of papers citing papers by Michael Orshansky

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Michael Orshansky. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Michael Orshansky. The network helps show where Michael Orshansky may publish in the future.

Co-authorship network of co-authors of Michael Orshansky

This figure shows the co-authorship network connecting the top 25 collaborators of Michael Orshansky. A scholar is included among the top collaborators of Michael Orshansky based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Michael Orshansky. Michael Orshansky is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Orshansky, Michael, et al.. (2024). SoK Paper: Power Side-Channel Malware Detection. 1–9. 1 indexed citations

Deng, Zihao & Michael Orshansky. (2022). Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). 712–717. 6 indexed citations

Jin, Miao, Andreas Gerstlauer, & Michael Orshansky. (2014). Multi-level approximate logic synthesis under general error constraints. International Conference on Computer Aided Design. 504–510. 29 indexed citations

Wang, Ye, Michael Orshansky, & Constantine Caramanis. (2014). Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization. 1–6. 16 indexed citations

Zheng, Tianhao, et al.. (2013). Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring. 229–234. 41 indexed citations

Jin, Miao, Andreas Gerstlauer, & Michael Orshansky. (2013). Approximate logic synthesis under general error magnitude and frequency constraints. International Conference on Computer Aided Design. 779–786. 53 indexed citations

Yousofshahi, Mona, Michael Orshansky, Kyongbum Lee, & Soha Hassoun. (2013). Probabilistic strain optimization under constraint uncertainty. BMC Systems Biology. 7(1). 29–29. 6 indexed citations

Orshansky, Michael, et al.. (2013). Novel strong PUF based on nonlinearity of MOSFET subthreshold operation. 13–18. 45 indexed citations

Banerjee, Shayak, et al.. (2010). A methodology for propagating design tolerances to shape tolerances for use in manufacturing. Design, Automation, and Test in Europe. 1273–1278. 4 indexed citations

10.

Banerjee, Shayak, Kanak Agarwal, & Michael Orshansky. (2010). Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects. 6154. 1–4. 2 indexed citations

11.

Banerjee, Shayak, et al.. (2009). Compensating non-optical effects using electrically driven optical proximity correction. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 7275. 72750E–72750E. 2 indexed citations

12.

Banerjee, Shayak, et al.. (2008). Electrically driven optical proximity correction based on linear programming. International Conference on Computer Aided Design. 473–479. 12 indexed citations

13.

Devgan, Anirudh, et al.. (2007). A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26(10). 1790–1802. 16 indexed citations

14.

Orshansky, Michael, Sani Nassif, & Duane S. Boning. (2006). Design for Manufacturability and Statistical Design: A Comprehensive Approach. Springer eBooks. 27 indexed citations

15.

Orshansky, Michael, Linda Milor, & Chenming Hu. (2004). Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction. IEEE Transactions on Semiconductor Manufacturing. 17(1). 2–11. 83 indexed citations

16.

Nguyen, David T., Abhijit Davare, Michael Orshansky, et al.. (2003). Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic IC design]. 158–163. 42 indexed citations

17.

Orshansky, Michael, Costas J. Spanos, & Chenming Hu. (2003). Circuit performance variability decomposition. 40. 10–13. 16 indexed citations

18.

Orshansky, Michael, Linda Milor, Pinhong Chen, Kurt Keutzer, & Chenming Hu. (2002). Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21(5). 544–553. 118 indexed citations

19.

Orshansky, Michael & Kurt Keutzer. (2002). A general probabilistic framework for worst case timing analysis. Proceedings - ACM IEEE Design Automation Conference. 8 indexed citations

20.

Orshansky, Michael, et al.. (1999). Direct sampling methodology for statistical analysis of scaled CMOS technologies. IEEE Transactions on Semiconductor Manufacturing. 12(4). 403–408. 22 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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