Michael Orshansky

5.4k citations

120 papers · 4.1k indexed · 2 hit papers · h-index 33

Hardware and Architecture top 0.2%
- VLSI and Analog Circuit Testing 30
- Physical Unclonable Functions (PUFs) and Hardware Security 17
Electrical and Electronic Engineering top 1%
- Low-power high-performance VLSI design 57
- VLSI and FPGA Design Techniques 36
- Advancements in Semiconductor Devices and Circuit Design 25
- Integrated Circuits and Semiconductor Failure Analysis 20
- Semiconductor materials and devices 18
- Radiation Effects in Electronics 15
Computer Networks and Communications top 5%
Computational Theory and Mathematics top 2%
Signal Processing top 5%

Co-authors: Jie Han Kurt Keutzer Andreas Gerstlauer Bin Zhang Chenming Hu Dennis Sylvester Takashi Satō Yu Cao
Cited by: Hardware and Architecture Electrical and Electronic Engineering Computer Networks and Communications
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (5 papers)IEEE Transactions on Semiconductor Manufacturing (2 papers)Journal of Micro/Nanolithography MEMS and MOEMS (2 papers)
Partner nations: United States Italy Canada

In The Last Decade

Michael Orshansky

119 papers receiving 3.9k citations

Hit Papers

align trajectories log scale

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

2013 Approximate computing: An emerging paradigm for energy-efficient design
2002 New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Peers

Countries citing papers authored by Michael Orshansky

Since Specialization

Citations

This map shows the geographic impact of Michael Orshansky's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Michael Orshansky with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Michael Orshansky more than expected).

Fields of papers citing papers by Michael Orshansky

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Michael Orshansky. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Michael Orshansky. The network helps show where Michael Orshansky may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Michael Orshansky, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Michael Orshansky Line = papers co-authored together Michael Orshansky links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	SoK Paper: Power Side-Channel Malware Detection Zhang Mucun,Placido dos Santos,Connie Vollebekk,Michael Orshansky,Kyle Blount,Andreas Gerstlauer	2024	1
2	Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) ·Zihao Deng,Michael Orshansky	2022	6
3	Multi-level approximate logic synthesis under general error constraints International Conference on Computer Aided Design ·Miao Jin,Andreas Gerstlauer,Michael Orshansky	2014	29
4	Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization Ye Wang,Michael Orshansky,Constantine Caramanis	2014	16
5	Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring Tianhao Zheng,Ma-Lian Chia,Michael Orshansky,Mattan Erez	2013	41
6	Approximate logic synthesis under general error magnitude and frequency constraints International Conference on Computer Aided Design ·Miao Jin,Andreas Gerstlauer,Michael Orshansky	2013	53
7	Probabilistic strain optimization under constraint uncertainty BMC Systems Biology ·Mona Yousofshahi,Michael Orshansky,Kyongbum Lee,Soha Hassoun	2013	6
8	Novel strong PUF based on nonlinearity of MOSFET subthreshold operation Saji John Konnully,Michael Orshansky	2013	45
9	A methodology for propagating design tolerances to shape tolerances for use in manufacturing Design, Automation, and Test in Europe ·Shayak Banerjee,Kanak Agarwal,Z. Yu. Redgepova,Sani Nassif,Michael Orshansky	2010	4
10	Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects Shayak Banerjee,Kanak Agarwal,Michael Orshansky	2010	2
11	Compensating non-optical effects using electrically driven optical proximity correction Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Shayak Banerjee,Kanak Agarwal,Önder Saatçi,S.G. Shapovalov,Lars W. Liebmann,Michael Orshansky	2009	2
12	Electrically driven optical proximity correction based on linear programming International Conference on Computer Aided Design ·Shayak Banerjee,S.G. Shapovalov,Lars W. Liebmann,Michael Orshansky	2008	12
13	A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Dhea Riqqa Nabila,Anirudh Devgan,Michael Orshansky,C.H. Shepherd-Themistocleous	2007	16
14	Design for Manufacturability and Statistical Design: A Comprehensive Approach Springer eBooks ·Michael Orshansky,Sani Nassif,Duane S. Boning	2006	27
15	Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction IEEE Transactions on Semiconductor Manufacturing ·Michael Orshansky,Linda Milor,Chenming Hu	2004	83
16	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic IC design] David T. Nguyen,Abhijit Davare,Michael Orshansky,David Chinnery,Brandon Thompson,Kurt Keutzer	2003	42
17	Circuit performance variability decomposition Michael Orshansky,Costas J. Spanos,Chenming Hu	2003	16
18	Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Michael Orshansky,Linda Milor,Pinhong Chen,Kurt Keutzer,Chenming Hu	2002	118
19	A general probabilistic framework for worst case timing analysis Proceedings - ACM IEEE Design Automation Conference ·Michael Orshansky,Kurt Keutzer	2002	8
20	Direct sampling methodology for statistical analysis of scaled CMOS technologies IEEE Transactions on Semiconductor Manufacturing ·Michael Orshansky,عبدالمنعم عمر,Chenming Hu	1999	22

About Michael Orshansky

Michael Orshansky is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Statistics, Probability and Uncertainty, Computational Theory and Mathematics and Artificial Intelligence, having authored 120 papers that have together received 4.1k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (57 papers), VLSI and FPGA Design Techniques (36 papers), VLSI and Analog Circuit Testing (30 papers), Advancements in Semiconductor Devices and Circuit Design (25 papers), Integrated Circuits and Semiconductor Failure Analysis (20 papers), Semiconductor materials and devices (18 papers), Physical Unclonable Functions (PUFs) and Hardware Security (17 papers) and Radiation Effects in Electronics (15 papers). The work is most often cited by research in Hardware and Architecture (2.0k citations), Electrical and Electronic Engineering (3.6k citations), Computer Networks and Communications (425 citations), Computational Theory and Mathematics (271 citations) and Signal Processing (128 citations). Michael Orshansky has collaborated with scholars based in United States, Italy and Canada. Frequent co-authors include Jie Han, Kurt Keutzer, Andreas Gerstlauer, Bin Zhang, Chenming Hu, Dennis Sylvester, Takashi Satō, Yu Cao, Miao Jin and Wei‐Shen Wang. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Semiconductor Manufacturing, Journal of Micro/Nanolithography MEMS and MOEMS, ACM Transactions on Embedded Computing Systems and IEEE Transactions on Computers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact