Sachin Taneja

433 total citations
26 papers, 314 citations indexed

About

Sachin Taneja is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Artificial Intelligence. According to data from OpenAlex, Sachin Taneja has authored 26 papers receiving a total of 314 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Hardware and Architecture, 13 papers in Electrical and Electronic Engineering and 12 papers in Artificial Intelligence. Recurrent topics in Sachin Taneja's work include Physical Unclonable Functions (PUFs) and Hardware Security (18 papers), Cryptographic Implementations and Security (10 papers) and Security and Verification in Computing (8 papers). Sachin Taneja is often cited by papers focused on Physical Unclonable Functions (PUFs) and Hardware Security (18 papers), Cryptographic Implementations and Security (10 papers) and Security and Verification in Computing (8 papers). Sachin Taneja collaborates with scholars based in Singapore, United States and India. Sachin Taneja's co-authors include Massimo Alioto, Anastacia B. Alvarez, Muhammad Naveed Aman, Biplab Sikdar, Kee Chaing Chua, Sanu Mathew, Raghavan Kumar, Vivek De, Avinash L. Varna and Carlos Tokunaga and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Internet of Things Journal and Journal of Anaesthesiology Clinical Pharmacology.

In The Last Decade

Sachin Taneja

23 papers receiving 307 citations

Peers

Countries citing papers authored by Sachin Taneja

Since Specialization

Citations

This map shows the geographic impact of Sachin Taneja's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sachin Taneja with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sachin Taneja more than expected).

Fields of papers citing papers by Sachin Taneja

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sachin Taneja. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sachin Taneja. The network helps show where Sachin Taneja may publish in the future.

Co-authorship network of co-authors of Sachin Taneja

This figure shows the co-authorship network connecting the top 25 collaborators of Sachin Taneja. A scholar is included among the top collaborators of Sachin Taneja based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Sachin Taneja. Sachin Taneja is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work	Indexed citations
1	A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS 2025 ·IEEE Journal of Solid-State Circuits ·Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew	0
2	UFC: A Unified Accelerator for Fully Homomorphic Encryption 2024 ·Minxuan Zhou, Yujin Nam, Xuan Wang, (unknown), Chris Wilkerson, Raghavan Kumar, Sachin Taneja, Sanu Mathew, Rosario Cammarota, Tajana Rosing	1
3	A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS 2024 ·Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew	0
4	Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm 2023 ·Animesh Gupta, (unknown), (unknown), Sachin Taneja, Massimo Alioto	1
5	15.5 A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS 2023 ·Raghavan Kumar, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew	9
6	A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%–99.99% Error Coverage in Intel 4 CMOS 2023 ·IEEE Journal of Solid-State Circuits ·Raghavan Kumar, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew	6
7	A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS 2022 ·2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Raghavan Kumar, Vikram Suresh, Sachin Taneja, Mark Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew	2
8	In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security 2021 ·IEEE Journal of Solid-State Circuits ·Sachin Taneja, (unknown), Massimo Alioto	41
9	SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm² and 749-1,459 TOPS/W in 28nm 2021 ·(unknown), Sachin Taneja, Massimo Alioto	2
10	PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion 2021 ·IEEE Journal of Solid-State Circuits ·Sachin Taneja, Massimo Alioto	20
11	SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm² and 749-1,459 TOPS/W in 28nm 2021 ·(unknown), Sachin Taneja, Massimo Alioto	1
12	Fully Synthesizable Unified True Random Number Generator and Cryptographic Core 2021 ·IEEE Journal of Solid-State Circuits ·Sachin Taneja, Massimo Alioto	15
13	Fully Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction, and Utilization Within the Same Cryptographic Core 2020 ·IEEE Solid-State Circuits Letters ·Sachin Taneja, Massimo Alioto	4
14	Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper) 2019 ·National University of Singapore ·Massimo Alioto, Sachin Taneja	12
15	PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion 2019 ·Sachin Taneja, Massimo Alioto	2
16	Effect of a low-dose dexmedetomidine infusion on intraoperative hemodynamics, anesthetic requirements and recovery profile in patients undergoing lumbar spine surgery 2019 ·Journal of Anaesthesiology Clinical Pharmacology ·(unknown), Sachin Taneja, (unknown), Sunil Katyal, Isha Garg, (unknown)	4
17	Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm 2018 ·IEEE Journal of Solid-State Circuits ·Sachin Taneja, Anastacia B. Alvarez, Massimo Alioto	77
18	Occupational Stress in the Indian Army Oncology Nursing Workforce: A Cross-sectional Study 2018 ·Asia-Pacific Journal of Oncology Nursing ·(unknown), (unknown), (unknown), Pradeep Jaiswal, Sachin Taneja, (unknown), (unknown)	9
19	A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8–1.0V in 40nm 2017 ·Sachin Taneja, Anastacia B. Alvarez, (unknown), Massimo Alioto	2
20	A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology 2015 ·Vaibhav Verma, Sachin Taneja, (unknown), Sanjeev Jain	1

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact