Yih Wang

3.4k citations

62 papers · 2.3k · 1 hit paper · h-index 24

Impact in

Hardware and Architecture top 1%
- Parallel Computing and Optimization Techniques
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 2%
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- VLSI and FPGA Design Techniques

Papers in

Electrical and Electronic Engineering 57
- Semiconductor materials and devices 44
- Advancements in Semiconductor Devices and Circuit Design 30
- Low-power high-performance VLSI design 27
- Advanced Memory and Neural Computing 19
- Ferroelectric and Negative Capacitance Devices 16
- Integrated Circuits and Semiconductor Failure Analysis 6
- 3D IC and TSV technologies 4
Hardware and Architecture 8
- Parallel Computing and Optimization Techniques 5

Co-authors: Fatih Hamzaoglu (24 shared papers)M. Bohr (12 shared papers)B. Zheng (4 shared papers)Daniel Murray (4 shared papers)Hung-Jen Liao (7 shared papers)Mahmut E. Sinangil (4 shared papers)Dar Sun (4 shared papers)Uma Bhattacharya (5 shared papers)
Journals: IEEE Journal of Solid-State Circuits (10 papers)IEEE Transactions on Electron Devices (5 papers)Electric Power Systems Research (1 paper)IEEE Solid-State Circuits Magazine (1 paper)Journal of the European Ceramic Society (1 paper)
Partner nations: United States Taiwan South Korea

In The Last Decade

Yih Wang

58 papers receiving 2.3k citations

Yih Wang's Hit Papers

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16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications 2021 · 227 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2021 16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Peers

Countries citing papers authored by Yih Wang

Since Specialization

Citations

This map shows the geographic impact of Yih Wang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yih Wang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yih Wang more than expected).

Fields of papers citing papers by Yih Wang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yih Wang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yih Wang. The network helps show where Yih Wang may publish in the future.

Co-authors

The 25 scholars most cited alongside Yih Wang, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Yih Wang Line = papers co-authored together Yih Wang links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 62 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang	2020	255
2	A 3-GHz 70mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply Kedong Zhang, Uma Bhattacharya, Z. Chen, Fatih Hamzaoglu, Daniel Murray, N. Vallepalli, Yih Wang, B. Zheng, M. Bohr	2005	233
3	16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yulin Chen, Chieh-Pu Lo, C.W. Lu, H. Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan‐Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng‐Fan Chang, Tsung-Yung Jonathan Chang Hit paper breakdown →	2021	227
4	A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply IEEE Journal of Solid-State Circuits ·(unknown), U.K. Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, N. Vallepalli, Yih Wang, B. Zheng, M. Bohr	2005	183
5	SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction IEEE Journal of Solid-State Circuits ·Kedong Zhang, Uma Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, N. Vallepalli, Yih Wang, B. Zheng, M. Bohr	2005	150
6	A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations 2022 IEEE International Solid- State Circuits Conference (ISSCC) ·Hidehiro Fujiwara, H. Mori, Wei-Chang Zhao, Mei‐Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan‐Li Chou, Mahmut E. Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	2022	142
7	A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS IEEE Journal of Solid-State Circuits ·Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang	2020	125
8	A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V<inf>MIN</inf>-enhancing assist circuitry Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, (unknown), Kaizad Mistry, M. Bohr	2012	69
9	A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology IEEE Journal of Solid-State Circuits ·Fatih Hamzaoglu, (unknown), Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, A. Pavlov, Ken Smits, M. Bohr	2009	65
10	SRAM design on 65nm CMOS technology with integrated leakage reduction scheme Kedong Zhang, Uma Bhattacharya, Z. Chen, Fatih Hamzaoglu, Daniel Murray, N. Vallepalli, Yih Wang, B. Zheng, M. Bohr	2004	63
11	A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation IEEE Journal of Solid-State Circuits ·Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, (unknown)	2010	58
12	A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update H. Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao‐Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan‐Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	2023	57
13	A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry IEEE Journal of Solid-State Circuits ·Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, (unknown), Kaizad Mistry, M. Bohr	2012	55
14	A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications IEEE Journal of Solid-State Circuits ·Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, W. Hafez, Chia-Hong Jan, Pramod Kolar, S. Kulkarni, Jiefeng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, (unknown), M. Bohr	2008	49
15	13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology Fatih Hamzaoglu, Ümüt Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, N. Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, (unknown), Yih Wang, (unknown)	2014	48
16	A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management IEEE Journal of Solid-State Circuits ·Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, (unknown), M. Bohr	2010	39
17	Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM Yih Wang, Eric Karl, Mesut Meterelliyoz, Fatih Hamzaoglu, Yong-Gee Ng, Swaroop Ghosh, Liqiong Wei, Uddalak Bhattacharya, (unknown)	2011	37
18	A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management Yih Wang, Uma Bhattacharya, Fatih Hamzaoglu, P. Kolar, Yat Hon Ng, Lili Wei, Yu Zhang, Kedong Zhang, M. Bohr	2009	36
19	33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, C.W. Lu, Yulin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng‐Hsiung Kuo, Tan‐Li Chou, Chia-Yu Wang, J. J. Wu, (unknown), Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang	2023	34
20	A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-¿ Metal-Gate CMOS Technology Fatih Hamzaoglu, (unknown), Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, A. Pavlov, Ken Smits, M. Bohr	2008	31

About Yih Wang

Yih Wang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Materials Chemistry, Computer Networks and Communications and Surfaces, Coatings and Films, having authored 62 papers that have together received 2.3k indexed citations. Recurring topics across this work include Semiconductor materials and devices (44 papers), Advancements in Semiconductor Devices and Circuit Design (30 papers), Low-power high-performance VLSI design (27 papers), Advanced Memory and Neural Computing (19 papers), Ferroelectric and Negative Capacitance Devices (16 papers), Integrated Circuits and Semiconductor Failure Analysis (6 papers), Parallel Computing and Optimization Techniques (5 papers) and 3D IC and TSV technologies (4 papers). The work is most often cited by research in Hardware and Architecture (521 citations), Electrical and Electronic Engineering (2.1k citations), Computer Networks and Communications (175 citations), Artificial Intelligence (163 citations) and Computational Mathematics (3 citations). Yih Wang has collaborated with scholars based in United States, Taiwan and South Korea. Frequent co-authors include Fatih Hamzaoglu, M. Bohr, B. Zheng, Daniel Murray, Hung-Jen Liao, Mahmut E. Sinangil, Dar Sun, Uma Bhattacharya, Kedong Zhang and Zhanping Chen. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices, Electric Power Systems Research, IEEE Solid-State Circuits Magazine and Journal of the European Ceramic Society.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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Yih Wang's Hit Papers

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About Yih Wang

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