S. Kulkarni

1.3k total citations
33 papers, 957 citations indexed

About

S. Kulkarni is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, S. Kulkarni has authored 33 papers receiving a total of 957 indexed citations (citations by other indexed papers that have themselves been cited), including 33 papers in Electrical and Electronic Engineering, 7 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in S. Kulkarni's work include Low-power high-performance VLSI design (17 papers), Advancements in Semiconductor Devices and Circuit Design (15 papers) and Semiconductor materials and devices (11 papers). S. Kulkarni is often cited by papers focused on Low-power high-performance VLSI design (17 papers), Advancements in Semiconductor Devices and Circuit Design (15 papers) and Semiconductor materials and devices (11 papers). S. Kulkarni collaborates with scholars based in United States. S. Kulkarni's co-authors include Dennis Sylvester, Pinaki Mazumder, Mukul Bhattacharya, G.I. Haddad, Jian Sun, David Blaauw, Leon Stok, David Z. Pan, Ruchir Puri and David S. Kung and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

S. Kulkarni

33 papers receiving 901 citations

Peers

Countries citing papers authored by S. Kulkarni

Since Specialization

Citations

This map shows the geographic impact of S. Kulkarni's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Kulkarni with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Kulkarni more than expected).

Fields of papers citing papers by S. Kulkarni

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Kulkarni. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Kulkarni. The network helps show where S. Kulkarni may publish in the future.

Co-authorship network of co-authors of S. Kulkarni

This figure shows the co-authorship network connecting the top 25 collaborators of S. Kulkarni. A scholar is included among the top collaborators of S. Kulkarni based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Kulkarni. S. Kulkarni is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process 2020 ·IEEE Solid-State Circuits Letters ·S. Kulkarni, (unknown), (unknown), Fang‐Lin Chao, Yao‐Feng Chang, (unknown), (unknown), (unknown), (unknown), Jiabo Li, (unknown), B. Sell, Uddalak Bhattacharya, Ying Zhang	6
2	Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET Technology 2019 ·(unknown), S. Kulkarni, (unknown), (unknown), (unknown), (unknown), Guannan Liu, M Armstrong, (unknown), (unknown), S. Ramey, Uddalak Bhattacharya, B. Sell, Ying Zhang	3
3	A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming 2017 ·IEEE Journal of Solid-State Circuits ·Zhanping Chen, S. Kulkarni, Vincent E. Dorgan, (unknown), Lei Jiang, Uddalak Bhattacharya	6
4	A 0.9um²1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating 2016 ·(unknown), S. Kulkarni, Vincent E. Dorgan, Uma Bhattacharya, (unknown)	2
5	A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm<sup>2</sup> 1T1C bit cell 2012 ·S. Kulkarni, Sangwoo Pae, Zhanping Chen, W. Hafez, (unknown), Anisur Rahman, (unknown), Uddalak Bhattacharya, (unknown), Guomin Zhang	3
6	High-density 3-D metal-fuse PROM featuring 1.37µm 2 1T1R bit cell in 32nm high-k metal-gate CMOS technology 2009 ·S. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, (unknown), Guomin Zhang	4
7	Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias 2008 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·S. Kulkarni, Dennis Sylvester, David Blaauw	37
8	A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications 2008 ·IEEE Journal of Solid-State Circuits ·Yuxiao Wang, (unknown), Uddalak Bhattacharya, Zhanping Chen, (unknown), Fatih Hamzaoglu, W. Hafez, (unknown), Pramod Kolar, S. Kulkarni, Jiefeng Lin, Yong-Gee Ng, (unknown), Liqiong Wei, Ying Zhang, Guomin Zhang, M. Bohr	49
9	A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications 2007 ·Yuxiao Wang, Jiefeng Lin, Yat Hon Ng, I. Post, (unknown), Yu Zhang, Kedong Zhang, M. Bohr, (unknown), Uma Bhattacharya, (unknown), Fatih Hamzaoglu, W. Hafez, C.-H. Jan, (unknown), S. Kulkarni	25
10	Power distribution techniques for dual vdd circuits 2006 ·S. Kulkarni, Dennis Sylvester	4
11	Power distribution techniques for dual VDD circuits 2006 ·S. Kulkarni, Dennis Sylvester	8
12	A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering 2006 ·Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design ·S. Kulkarni, Dennis Sylvester, David Blaauw	17
13	High Performance Level Conversion for Dual Design 2004 ·S. Kulkarni, Dennis Sylvester	1
14	A new algorithm for improved VDD assignment in low power dual VDD systems 2004 ·S. Kulkarni, (unknown), Dennis Sylvester	41
15	Pushing ASIC performance in a power envelope 2003 ·Ruchir Puri, Leon Stok, John Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, S. Kulkarni	106
16	Pushing ASIC performance in a power envelope 2003 ·Ruchir Puri, Leon Stok, John R. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Kumar Srivastava, S. Kulkarni	44
17	An implementation of a 32-bit ARM processor using dual power supplies and dual threshold voltages 2003 ·(unknown), S. Kulkarni, (unknown), Ashish Srivastava, Dennis Sylvester, David Blaauw	4
18	A high-speed 32-bit parallel correlator for spread spectrum communication 2002 ·S. Kulkarni, (unknown), G.I. Haddad	3
19	CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices 2001 ·IEEE Journal of Solid-State Circuits ·(unknown), Mukul Bhattacharya, S. Kulkarni, Pinaki Mazumder	22
20	A physical design tool for built-in self-repairable static RAMs 1999 ·Kanad Chakraborty, Anurag Gupta, (unknown), S. Kulkarni, Pinaki Mazumder	5

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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