Yen-Huei Chen

1.2k total citations · 1 hit paper
27 papers, 865 citations indexed

About

Yen-Huei Chen is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Yen-Huei Chen has authored 27 papers receiving a total of 865 indexed citations (citations by other indexed papers that have themselves been cited), including 25 papers in Electrical and Electronic Engineering, 6 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in Yen-Huei Chen's work include Semiconductor materials and devices (20 papers), Advancements in Semiconductor Devices and Circuit Design (17 papers) and Low-power high-performance VLSI design (12 papers). Yen-Huei Chen is often cited by papers focused on Semiconductor materials and devices (20 papers), Advancements in Semiconductor Devices and Circuit Design (17 papers) and Low-power high-performance VLSI design (12 papers). Yen-Huei Chen collaborates with scholars based in Taiwan, United States and Japan. Yen-Huei Chen's co-authors include Hung-Jen Liao, Hidehiro Fujiwara, Jonathan Chang, Tsung-Yung Jonathan Chang, Meng‐Fan Chang, Yu-Der Chih, Dar Sun, Kerem Akarvardar, H. Mori and Tan‐Li Chou and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, 2022 IEEE International Solid- State Circuits Conference (ISSCC) and IEEE Conference Proceedings.

In The Last Decade

Yen-Huei Chen

25 papers receiving 839 citations

Hit Papers

16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based ... 2021 2026 2022 2024 2021 50 100 150 200

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Yen-Huei Chen Taiwan 13 785 224 83 74 56 27 865
Hidehiro Fujiwara Japan 15 875 1.1× 300 1.3× 107 1.3× 85 1.1× 68 1.2× 47 968
Dar Sun Taiwan 7 671 0.9× 191 0.9× 75 0.9× 112 1.5× 86 1.5× 8 746
Vinay Vashishtha United States 9 591 0.8× 229 1.0× 62 0.7× 60 0.8× 25 0.4× 19 702
Arindam Mallik Belgium 16 347 0.4× 194 0.9× 153 1.8× 40 0.5× 75 1.3× 41 527
Mahdi Nazm Bojnordi United States 12 364 0.5× 199 0.9× 169 2.0× 118 1.6× 85 1.5× 42 529
Tan‐Li Chou United States 16 755 1.0× 470 2.1× 86 1.0× 89 1.2× 52 0.9× 28 855
Xiulong Wu China 16 803 1.0× 237 1.1× 59 0.7× 62 0.8× 30 0.5× 118 866
Mehdi Saligane United States 15 471 0.6× 183 0.8× 57 0.7× 53 0.7× 47 0.8× 40 590
Pascal Meinerzhagen Switzerland 18 704 0.9× 163 0.7× 183 2.2× 50 0.7× 21 0.4× 51 762
Ik‐Joon Chang South Korea 17 1.2k 1.5× 362 1.6× 123 1.5× 62 0.8× 93 1.7× 70 1.3k

Countries citing papers authored by Yen-Huei Chen

Since Specialization
Citations

This map shows the geographic impact of Yen-Huei Chen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yen-Huei Chen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yen-Huei Chen more than expected).

Fields of papers citing papers by Yen-Huei Chen

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yen-Huei Chen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yen-Huei Chen. The network helps show where Yen-Huei Chen may publish in the future.

Co-authorship network of co-authors of Yen-Huei Chen

This figure shows the co-authorship network connecting the top 25 collaborators of Yen-Huei Chen. A scholar is included among the top collaborators of Yen-Huei Chen based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yen-Huei Chen. Yen-Huei Chen is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Fujiwara, Hidehiro, Chih‐Yu Lin, Yung‐Hsiang Lin, et al.. (2025). 29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. 500–502.
2.
Chang, Tsung-Yung Jonathan, Yen-Huei Chen, Po‐Sheng Wang, et al.. (2025). A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. 492–494.
5.
Wang, Yuxiao, Yen-Huei Chen, Y.D. Chih, et al.. (2023). High-Speed Embedded Memory for AI and High-Performance Compute. 1–4. 2 indexed citations
6.
Fujiwara, Hidehiro, H. Mori, Mei‐Chen Chuang, et al.. (2022). A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. 2022 IEEE International Solid- State Circuits Conference (ISSCC). 1–3. 134 indexed citations
7.
Chih, Yu-Der, Po-Hao Lee, Hidehiro Fujiwara, et al.. (2021). 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. 252–254. 206 indexed citations breakdown →
9.
Chang, Tsung-Yung Jonathan, Yen-Huei Chen, Po‐Sheng Wang, et al.. (2020). A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications. IEEE Journal of Solid-State Circuits. 56(1). 179–187. 22 indexed citations
10.
Fujiwara, Hidehiro, Chih‐Yu Lin, J.J. Liaw, et al.. (2019). 24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. 390–392. 14 indexed citations
12.
Chang, Jonathan, Hung-Jen Liao, Yu-Der Chih, et al.. (2017). Embedded memories for mobile, IoT, automotive and high performance computing. T26–T27. 8 indexed citations
13.
Fujiwara, Hidehiro, Liwen Wang, Yen-Huei Chen, et al.. (2016). A 64kb 16nm Asynchronous Disturb Current Free 2-Port SRAM with PMOS Pass-Gates for FinFET Technologies. IEICE technical report. Speech. 116(3). 17–20. 2 indexed citations
14.
Chen, Yen-Huei, et al.. (2016). A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V MIN applications. IEEE Conference Proceedings. 2016. 1–2. 1 indexed citations
15.
Fujiwara, Hidehiro, et al.. (2016). A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications. 185–188. 13 indexed citations
16.
Chen, Yen-Huei, et al.. (2014). A 16 nm 128 Mb SRAM in High-$\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. IEEE Journal of Solid-State Circuits. 50(1). 170–177. 113 indexed citations
17.
Sheu, B.J., Chih‐Sheng Chang, Yen-Huei Chen, et al.. (2013). Enabling circuit design using FinFETs through close ecosystem collaboration. 6576615. 3 indexed citations
18.
Chen, Yen-Huei, Dar Sun, Hung-Jen Liao, et al.. (2012). Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM. IEEE Journal of Solid-State Circuits. 47(4). 969–980. 14 indexed citations
19.
Chang, Meng‐Fan, Pi-Feng Chiu, Yen-Huei Chen, et al.. (2011). A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms. 74–75. 10 indexed citations
20.
Wu, Jui-Jen, Yen-Huei Chen, Meng‐Fan Chang, et al.. (2011). A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. IEEE Journal of Solid-State Circuits. 46(4). 815–827. 65 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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