Tan‐Li Chou

1.3k citations

28 papers · 855 indexed · 1 hit paper · h-index 16

Impact in

Hardware and Architecture top 1%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
Electrical and Electronic Engineering top 5%
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- VLSI and FPGA Design Techniques
- Semiconductor materials and devices

Papers in

Hardware and Architecture 23
- VLSI and Analog Circuit Testing 18
- Parallel Computing and Optimization Techniques 4
Electrical and Electronic Engineering 28
- Low-power high-performance VLSI design 21
- VLSI and FPGA Design Techniques 18
- Ferroelectric and Negative Capacitance Devices 5
- Advanced Memory and Neural Computing 4
- Radiation Effects in Electronics 3

Co-authors: Kaushik Roy Tsung-Yung Jonathan Chang Yu-Der Chih Chia-Fu Lee H. Mori Hidehiro Fujiwara Yuxiao Wang Kerem Akarvardar
Journals: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2 papers)Integrated Computer-Aided Engineering (1 paper)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1 paper)IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences (1 paper)2022 IEEE International Solid- State Circuits Conference (ISSCC) (1 paper)
Partner nations: United States Taiwan

In The Last Decade

Tan‐Li Chou

28 papers receiving 829 citations

Hit Papers

align trajectories log scale

16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications 2021 · 206 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2021 16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Peers

Countries citing papers authored by Tan‐Li Chou

Since Specialization

Citations

This map shows the geographic impact of Tan‐Li Chou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tan‐Li Chou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tan‐Li Chou more than expected).

Fields of papers citing papers by Tan‐Li Chou

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Tan‐Li Chou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tan‐Li Chou. The network helps show where Tan‐Li Chou may publish in the future.

Co-authors

The 25 scholars most cited alongside Tan‐Li Chou, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Tan‐Li Chou Line = papers co-authored together Tan‐Li Chou links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update H. Mori, Meshal Fawaz Aldhamen, Amalia Hasanah, Chia-Fu Lee, Edwin Ankuash, Yirong Yin, 陳里菜, P.J. van der Doef, Hernane Guimarães dos Santos, G. Gridel, Kerem Akarvardar, Tan‐Li Chou, Hidehiro Fujiwara, Yuxiao Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	2023	52
2	33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, R. D. Syubaev, Eilish Brown, Cheng-Han Lu, Yulin Chen, Chieh-Pu Lo, Mustafa Eid, Gaurav Jain, Tan‐Li Chou, Chia-Yu Wang, Susan Majdak, Ruo‐Qian Wang, Harry Chuang, Yuxiao Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang	2023	31
3	A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Chia-Fu Lee, Cheng-Han Lu, Amalia Hasanah, H. Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan‐Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang	2022	46
4	A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations 2022 IEEE International Solid- State Circuits Conference (ISSCC) ·Hidehiro Fujiwara, H. Mori, Meshal Fawaz Aldhamen, Mei‐Chen Chuang, Rawan Naous, Yirong Yin, 陳里菜, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan‐Li Chou, Mahmut E. Sinangil, Yuxiao Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	2022	134
5	16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yulin Chen, Chieh-Pu Lo, Cheng-Han Lu, H. Mori, Meshal Fawaz Aldhamen, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan‐Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yuxiao Wang, Meng‐Fan Chang, Tsung-Yung Jonathan Chang Hit paper breakdown →	2021	206
6	Estimation of sequential circuit activity considering spatial and temporal correlations Tan‐Li Chou, Kaushik Roy	2002	11
7	Sensitivity of power dissipation to uncertainties in primary input specification 高橋志のぶ, Kaushik Roy, Tan‐Li Chou	2002	3
8	Design of low power digital systems Kaushik Roy, Ranjan Roy, Tan‐Li Chou	2002	2
9	Accurate estimation of power dissipation in CMOS sequential circuits Tan‐Li Chou, Kaushik Roy	2002	8
10	Statistical estimation of sequential circuit activity Tan‐Li Chou, Barbara E. Pommier	2002	17
11	Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion International Conference on Computer Aided Design ·Etry Mike, Tan‐Li Chou, Martin D. F. Wong, A. Aziz	2001	1
12	Integrated power supply planning and floorplanning Christian Pérez González, Hung-Ming Chen, Tan‐Li Chou, Adnan Aziz, Martin D. F. Wong	2001	20
13	Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion Christian Pérez González, Tan‐Li Chou, Adnan Aziz, Martin D. F. Wong	2000	47
14	Statistical Estimation of CMOS Circuit Activity under Probabilistic Delays (Special Section on VLSI Design and CAD Algorithms) IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ·Tan‐Li Chou, Kaushik Roy	1997	1
15	Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs International Conference on Computer Aided Design ·Zhanping Chen, Kaushik Roy, Tan‐Li Chou	1997	28
16	Accurate power estimation of CMOS sequential circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Tan‐Li Chou, Kaushik Roy	1996	35
17	Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Tan‐Li Chou, Kaushik Roy	1996	19
18	Statistical estimation of sequential circuit activity International Conference on Computer Aided Design ·Tan‐Li Chou, Kaushik Roy	1995	37
19	Estimation of circuit activity considering signal correlations and simultaneous switching International Conference on Computer Aided Design ·Tan‐Li Chou, Kaushik Roy, Sharat C. Prasad	1994	63
20	Estimation Of Circuit Activity Considering Signal Correlations And Simultaneous Switching IEEE/ACM International Conference on Computer-Aided Design ·Tan‐Li Chou, Kaushik Roy, Sylvie Ouellet	1994	29

About Tan‐Li Chou

Tan‐Li Chou is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Statistics, Probability and Uncertainty, Computer Networks and Communications and Computational Theory and Mathematics, having authored 28 papers that have together received 855 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (21 papers), VLSI and FPGA Design Techniques (18 papers), VLSI and Analog Circuit Testing (18 papers), Ferroelectric and Negative Capacitance Devices (5 papers), Parallel Computing and Optimization Techniques (4 papers), Advanced Memory and Neural Computing (4 papers), Radiation Effects in Electronics (3 papers) and Interconnection Networks and Systems (2 papers). The work is most often cited by research in Hardware and Architecture (470 citations), Electrical and Electronic Engineering (755 citations), Computer Networks and Communications (86 citations), Artificial Intelligence (89 citations) and Computer Vision and Pattern Recognition (52 citations). Tan‐Li Chou has collaborated with scholars based in United States and Taiwan. Frequent co-authors include Kaushik Roy, Tsung-Yung Jonathan Chang, Yu-Der Chih, Chia-Fu Lee, H. Mori, Hidehiro Fujiwara, Yuxiao Wang, Kerem Akarvardar, Yen-Huei Chen and Hung-Jen Liao. Their work appears in journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Integrated Computer-Aided Engineering, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences and 2022 IEEE International Solid- State Circuits Conference (ISSCC).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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