Alberto Cestero
Impact in
- Hardware and Architecture top 5%
- Physical Unclonable Functions (PUFs) and Hardware Security
- Parallel Computing and Optimization Techniques
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- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
Papers in
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- Semiconductor materials and devices 7
- Advanced Memory and Neural Computing 5
- Advancements in Semiconductor Devices and Circuit Design 4
- Low-power high-performance VLSI design 4
- 3D IC and TSV technologies 3
- Ferroelectric and Negative Capacitance Devices 2
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- Physical Unclonable Functions (PUFs) and Hardware Security 4
- Co-authors
- T. Kirihata (11 shared papers)Subramanian S. Iyer (10 shared papers)Norman Robson (12 shared papers)John Safran (5 shared papers)Sami Rosenblatt (4 shared papers)D. Moy (5 shared papers)C. Kothandaraman (3 shared papers)Xiang Chen (1 shared paper)
- Journals
- IEEE Journal of Solid-State Circuits (4 papers)IEEE Solid-State Circuits Letters (1 paper)IEEE Transactions on Electron Devices (1 paper)2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) (1 paper)
- Partner nations
- United StatesIndiaNetherlands
In The Last Decade
Alberto Cestero
15 papers receiving 240 citations
Peers
Comparison fields: 5 of 21
- Hardware and Architecture 154
- Electrical and Electronic Engineering 217
- Cellular and Molecular Neuroscience 46
- Computer Networks and Communications 34
- Signal Processing 12
Countries citing papers authored by Alberto Cestero
This map shows the geographic impact of Alberto Cestero's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Alberto Cestero with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Alberto Cestero more than expected).
Fields of papers citing papers by Alberto Cestero
This network shows the impact of papers produced by Alberto Cestero. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Alberto Cestero. The network helps show where Alberto Cestero may publish in the future.
Co-authors
The 25 scholars most cited alongside Alberto Cestero, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2007 | 56 | |
| 2 | 2013 | 39 | |
| 3 | 2005 | 35 | |
| 4 | 2013 | 32 | |
| 5 | 2007 | 20 | |
| 6 | 3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype | 2011 | 16 |
| 7 | 2012 | 13 | |
| 8 | 2016 | 10 | |
| 9 | 2004 | 8 | |
| 10 | 2018 | 8 | |
| 11 | 2018 | 5 | |
| 12 | 2021 | 3 | |
| 13 | 2022 | 2 | |
| 14 | 2016 | 2 | |
| 15 | 2022 | 1 |
About Alberto Cestero
Alberto Cestero is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Cellular and Molecular Neuroscience, Biomedical Engineering and Computer Networks and Communications, having authored 15 papers that have together received 250 indexed citations. Recurring topics across this work include Semiconductor materials and devices (7 papers), Advanced Memory and Neural Computing (5 papers), Advancements in Semiconductor Devices and Circuit Design (4 papers), Physical Unclonable Functions (PUFs) and Hardware Security (4 papers), Low-power high-performance VLSI design (4 papers), Neuroscience and Neural Engineering (3 papers), 3D IC and TSV technologies (3 papers) and Ferroelectric and Negative Capacitance Devices (2 papers). The work is most often cited by research in Hardware and Architecture (154 citations), Electrical and Electronic Engineering (217 citations), Cellular and Molecular Neuroscience (46 citations), Computer Networks and Communications (34 citations) and Signal Processing (12 citations). Alberto Cestero has collaborated with scholars based in United States, India and Netherlands. Frequent co-authors include T. Kirihata, Subramanian S. Iyer, Norman Robson, John Safran, Sami Rosenblatt, D. Moy, C. Kothandaraman, Xiang Chen, John Golz and P. Parries. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Solid-State Circuits Letters, IEEE Transactions on Electron Devices and 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.