Fotis Plessas
- Electrical and Electronic Engineering
- Hardware and Architecture top 5%
- Biomedical Engineering
- Artificial Intelligence
- Cellular and Molecular Neuroscience
- Co-authors
- Grigorios KalivasΚωνσταντίνος ΛιάκοςΓεώργιος ΓεωργακίλαςGeorge SouliotisSerafeim MoustakidisS. VlassisMichael BirbasPatrik Karlsson
- Topics
- Advancements in PLL and VCO Technologies (24 papers)Radio Frequency Integrated Circuit Design (21 papers)Analog and Mixed-Signal Circuit Design (12 papers)
- Journals
- Scientific ReportsElectronics LettersIEEE Transactions on Circuits and Systems I Regular Papers
- Partner nations
- GreeceUnited KingdomCzechia
In The Last Decade
Fotis Plessas
38 papers receiving 271 citations
Peers
Comparison fields: 5 of 37
- Electrical and Electronic Engineering 235
- Hardware and Architecture 88
- Biomedical Engineering 80
- Artificial Intelligence 30
- Cellular and Molecular Neuroscience 26
Countries citing papers authored by Fotis Plessas
This map shows the geographic impact of Fotis Plessas's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Fotis Plessas with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Fotis Plessas more than expected).
Fields of papers citing papers by Fotis Plessas
This network shows the impact of papers produced by Fotis Plessas. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Fotis Plessas. The network helps show where Fotis Plessas may publish in the future.
Co-authorship network of co-authors of Fotis Plessas
This figure shows the co-authorship network connecting the top 25 collaborators of Fotis Plessas. A scholar is included among the top collaborators of Fotis Plessas based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Fotis Plessas. Fotis Plessas is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 0 | |
| 2 | 1 | |
| 3 | 0 | |
| 4 | 1 | |
| 5 | 2 | |
| 6 | 8 | |
| 7 | 15 | |
| 8 | 3 | |
| 9 | 16 | |
| 10 | 2 | |
| 11 | 3 | |
| 12 | 4 | |
| 13 | 15 | |
| 14 | 4 | |
| 15 | 2 | |
| 16 | 7 | |
| 17 | 11 | |
| 18 | 2 | |
| 19 | 4 | |
| 20 | 2 |
About Fotis Plessas
Fotis Plessas is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Biomedical Engineering, having authored 44 papers that have together received 282 indexed citations. Recurring topics across this work include Advancements in PLL and VCO Technologies (24 papers), Radio Frequency Integrated Circuit Design (21 papers) and Analog and Mixed-Signal Circuit Design (12 papers). The work is most often cited by research in Hardware and Architecture (88 citations), Electrical and Electronic Engineering (235 citations) and Biomedical Engineering (80 citations). Fotis Plessas has collaborated with scholars based in Greece, United Kingdom and Czechia. Frequent co-authors include Grigorios Kalivas, Κωνσταντίνος Λιάκος, Γεώργιος Γεωργακίλας, George Souliotis, Serafeim Moustakidis, S. Vlassis, Michael Birbas, Patrik Karlsson, Nicolas Sklavos and Paris Kitsos. Their work appears in journals such as Scientific Reports, Electronics Letters and IEEE Transactions on Circuits and Systems I Regular Papers.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.