Brian Cline
- Electrical and Electronic Engineering top 2%
- Hardware and Architecture top 2%
- Biomedical Engineering
- Computer Networks and Communications top 10%
- Materials Chemistry
- Co-authors
- Greg YericSaurabh SinhaYu CaoL. ShifrenVikas ChandraVinay VashishthaChandarasekaran RamamurthyLawrence T. Clark
- Topics
- Semiconductor materials and devices (33 papers)3D IC and TSV technologies (22 papers)Low-power high-performance VLSI design (20 papers)
- Cited by
- Hardware and ArchitectureElectrical and Electronic EngineeringComputer Networks and Communications
- Journals
- IEEE Journal of Solid-State CircuitsIEEE Transactions on Electron DevicesIEEE Electron Device Letters
- Partner nations
- United StatesUnited KingdomBelgium
In The Last Decade
Brian Cline
58 papers receiving 1.6k citations
Hit Papers
Peers
Comparison fields: 5 of 56
- Electrical and Electronic Engineering 1.5k
- Hardware and Architecture 429
- Biomedical Engineering 169
- Computer Networks and Communications 153
- Materials Chemistry 90
Countries citing papers authored by Brian Cline
This map shows the geographic impact of Brian Cline's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Brian Cline with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Brian Cline more than expected).
Fields of papers citing papers by Brian Cline
This network shows the impact of papers produced by Brian Cline. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Brian Cline. The network helps show where Brian Cline may publish in the future.
Co-authorship network of co-authors of Brian Cline
This figure shows the co-authorship network connecting the top 25 collaborators of Brian Cline. A scholar is included among the top collaborators of Brian Cline based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Brian Cline. Brian Cline is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 5 | |
| 2 | 19 | |
| 3 | 10 | |
| 4 | 3 | |
| 5 | 7 | |
| 6 | 1 | |
| 7 | 28 | |
| 8 | 29 | |
| 9 | 8 | |
| 10 | 0 | |
| 11 | 7 | |
| 12 | 4 | |
| 13 | 25 | |
| 14 | 4 | |
| 15 | 15 | |
| 16 | 246 | |
| 17 | 4 | |
| 18 | 3 | |
| 19 | 19 | |
| 20 | 21 |
About Brian Cline
Brian Cline is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications, having authored 60 papers that have together received 1.6k indexed citations. Recurring topics across this work include Semiconductor materials and devices (33 papers), 3D IC and TSV technologies (22 papers) and Low-power high-performance VLSI design (20 papers). The work is most often cited by research in Hardware and Architecture (429 citations), Electrical and Electronic Engineering (1.5k citations) and Computer Networks and Communications (153 citations). Brian Cline has collaborated with scholars based in United States, United Kingdom and Belgium. Frequent co-authors include Greg Yeric, Saurabh Sinha, Yu Cao, L. Shifren, Vikas Chandra, Vinay Vashishtha, Chandarasekaran Ramamurthy, Lawrence T. Clark, David Blaauw and Dennis Sylvester. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and IEEE Electron Device Letters.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.