Holger Eisenreich

444 total citations
22 papers, 275 citations indexed

About

Holger Eisenreich is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Biomedical Engineering. According to data from OpenAlex, Holger Eisenreich has authored 22 papers receiving a total of 275 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Electrical and Electronic Engineering, 7 papers in Computer Networks and Communications and 6 papers in Biomedical Engineering. Recurrent topics in Holger Eisenreich's work include Low-power high-performance VLSI design (11 papers), Advancements in PLL and VCO Technologies (8 papers) and Interconnection Networks and Systems (6 papers). Holger Eisenreich is often cited by papers focused on Low-power high-performance VLSI design (11 papers), Advancements in PLL and VCO Technologies (8 papers) and Interconnection Networks and Systems (6 papers). Holger Eisenreich collaborates with scholars based in Germany, Canada and United Kingdom. Holger Eisenreich's co-authors include Sebastian Höppner, René Schüffny, Georg Ellguth, Dennis Walter, Stephan Henker, Christian Mayr, Stefan Scholze, Gerhard Fettweis, Jörg Schreiter and Thomas Hocker and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Transactions on Circuits & Systems II Express Briefs.

In The Last Decade

Holger Eisenreich

22 papers receiving 268 citations

Peers

Holger Eisenreich

EEE

CNC

Dennis Walter Germany

Georg Ellguth Germany

Rick Amerson United States

Thorsten Jungeblut Germany

Jan-Willem Weijers Belgium

Ashwin Sanjay Lele United States

Pravin Mane India

Jim Ignowski United States

Edouard Giacomin United States

Dennis Walter Germany

Holger Eisenreich

255 ×1.1

EEE

59 ×0.9

CNC

53 ×1.0

63 ×1.4

42 ×1.1

Citations per year, relative to Holger Eisenreich Holger Eisenreich (= 1×) peers Dennis Walter

Countries citing papers authored by Holger Eisenreich

Since Specialization

Citations

This map shows the geographic impact of Holger Eisenreich's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Holger Eisenreich with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Holger Eisenreich more than expected).

Fields of papers citing papers by Holger Eisenreich

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Holger Eisenreich. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Holger Eisenreich. The network helps show where Holger Eisenreich may publish in the future.

Co-authorship network of co-authors of Holger Eisenreich

This figure shows the co-authorship network connecting the top 25 collaborators of Holger Eisenreich. A scholar is included among the top collaborators of Holger Eisenreich based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Holger Eisenreich. Holger Eisenreich is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Scholze, Stefan, et al.. (2023). A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. 67–68. 2 indexed citations

Walter, Dennis, et al.. (2020). A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. 1–3. 9 indexed citations

Höppner, Sebastian, et al.. (2019). How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. 66–69. 20 indexed citations

Höppner, Sebastian, Holger Eisenreich, Dennis Walter, et al.. (2019). Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. IEEE Transactions on Circuits & Systems II Express Briefs. 67(10). 2159–2163. 23 indexed citations

Höppner, Sebastian, Dennis Walter, Thomas Hocker, et al.. (2015). An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. IEEE Journal of Solid-State Circuits. 50(3). 749–762. 17 indexed citations

Höppner, Sebastian, Holger Eisenreich, Georg Ellguth, et al.. (2014). A compact on-chip IR-drop measurement system in 28 nm CMOS technology. 1219–1222. 5 indexed citations

Arnold, Oliver, Tobias Seifert, Emil Matúš, et al.. (2014). 10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. 188–189. 20 indexed citations

Höppner, Sebastian, et al.. (2013). A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. IEEE Transactions on Circuits & Systems II Express Briefs. 60(11). 741–745. 36 indexed citations

Ellinger, Frank, Gerhard Fettweis, Corrado Carta, et al.. (2013). Power-efficient high-frequency integrated circuits and communication systems developed within Cool Silicon cluster project. 1–2. 2 indexed citations

10.

Matúš, Emil, Gerhard Fettweis, Holger Eisenreich, et al.. (2012). A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. 216–218. 11 indexed citations

11.

Höppner, Sebastian, et al.. (2012). A power management architecture for fast per-core DVFS in heterogeneous MPSoCs. 261–264. 16 indexed citations

12.

Walter, Dennis, Sebastian Höppner, Holger Eisenreich, et al.. (2012). A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. 180–182. 25 indexed citations

13.

Höppner, Sebastian, Stephan Henker, Holger Eisenreich, & René Schüffny. (2011). An open-loop clock generator for fast frequency scaling in 65nm CMOS technology. International Conference Mixed Design of Integrated Circuits and Systems. 264–269. 8 indexed citations

14.

Scholze, Stefan, Holger Eisenreich, Sebastian Höppner, et al.. (2011). A 32 GBit/s communication SoC for a waferscale neuromorphic system. Integration. 45(1). 61–75. 30 indexed citations

15.

Berthold, J., et al.. (2010). Low power design of the X-GOLD® SDR 20 baseband processor. Design, Automation, and Test in Europe. 792–793. 1 indexed citations

16.

Raab, W., et al.. (2010). Low power design of the X-GOLD® SDR 20 baseband processor. 792–793. 1 indexed citations

17.

Höppner, Sebastian, Dennis Walter, Holger Eisenreich, & René Schüffny. (2010). Efficient compensation of delay variations in high-speed network-on-chip data links. 55–58. 3 indexed citations

18.

Eisenreich, Holger, et al.. (2009). A novel ADPLL design using successive approximation frequency control. Microelectronics Journal. 40(11). 1613–1622. 15 indexed citations

19.

Mayr, Christian, Holger Eisenreich, Stephan Henker, & René Schüffny. (2008). Pulsed Multi-Layered Image Filtering: A Vlsi Implementation. Zenodo (CERN European Organization for Nuclear Research). 2 indexed citations

20.

Eisenreich, Holger, et al.. (2007). A programmable clock generator HDL softcore. 6. 1–4. 3 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact