Kaushik Vaidyanathan

447 citations

26 papers · 320 indexed · h-index 10

Co-authors: Larry Pileggi Renzhi Liu Bishnu Prasad Das Lars W. Liebmann Franz Franchetti Andrzej J. Strojwas Kafai Lai Daniel Morris
Topics: Advancements in Semiconductor Devices and Circuit Design (9 papers)Semiconductor materials and devices (9 papers)Advanced Memory and Neural Computing (8 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Cellular and Molecular Neuroscience
Journals: Journal of Micro/Nanolithography MEMS and MOEMS IEEE Journal on Exploratory Solid-State Computational Devices and CircuitsInternational Conference on Computer Aided Design
Partner nations: United States India

In The Last Decade

Kaushik Vaidyanathan

26 papers receiving 309 citations

Peers

Countries citing papers authored by Kaushik Vaidyanathan

Since Specialization

Citations

This map shows the geographic impact of Kaushik Vaidyanathan's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kaushik Vaidyanathan with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kaushik Vaidyanathan more than expected).

Fields of papers citing papers by Kaushik Vaidyanathan

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kaushik Vaidyanathan. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kaushik Vaidyanathan. The network helps show where Kaushik Vaidyanathan may publish in the future.

Co-authorship network of co-authors of Kaushik Vaidyanathan

This figure shows the co-authorship network connecting the top 25 collaborators of Kaushik Vaidyanathan. A scholar is included among the top collaborators of Kaushik Vaidyanathan based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kaushik Vaidyanathan. Kaushik Vaidyanathan is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Boreas: A Cost-Effective Mitigation Method for Advanced Hotspots using Machine Learning and Hardware Telemetry 2023 ·(unknown),(unknown),(unknown),(unknown),Kaushik Vaidyanathan,Mark Hempstead	1
2	HotGauge: A Methodology for Characterizing Advanced Hotspots in Modern and Next Generation Processors 2021 ·(unknown),(unknown),(unknown),(unknown),Kaushik Vaidyanathan,Mark Hempstead	10
3	Corrections to “Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin-Orbit Devices Toward 100-mV Logic” 2019 ·IEEE Journal on Exploratory Solid-State Computational Devices and Circuits ·Huichu Liu,Sasikanth Manipatruni,Daniel H. Morris,Kaushik Vaidyanathan,Dmitri E. Nikonov,Tanay Karnik,Ian A. Young	1
4	Closed yet Open DRAM: Achieving Low Latency and High Performance in DRAM Memory Systems 2018 ·Lavanya Subramanian,Kaushik Vaidyanathan,(unknown),(unknown),Tanay Karnik,Hong Wang	3
5	Improving Energy Efficiency of Low-Voltage Logic by Technology-Driven Design 2018 ·IEEE Journal on Exploratory Solid-State Computational Devices and Circuits ·Kaushik Vaidyanathan,Daniel H. Morris,Uygar E. Avci,Huichu Liu,Tanay Karnik,Hong Wang,Ian A. Young	4
6	Closed yet open DRAM 2018 ·Lavanya Subramanian,Kaushik Vaidyanathan,(unknown),Sreenivas Subramoney,Tanay Karnik,Hong Wang	3
7	Novel TFET circuits for high-performance energy-efficient heterogeneous MOSFET/TFET logic 2017 ·Daniel H. Morris,Uygar E. Avci,Kaushik Vaidyanathan,Huichu Liu,Tanay Karnik,Ian A. Young	3
8	Overcoming interconnect scaling challenges using novel process and design solutions to improve both high-speed and low-power computing modes 2017 ·Kaushik Vaidyanathan,Daniel H. Morris,Uygar E. Avci,(unknown),Lavanya Subramanian,Jayesh Gaur,Huichu Liu,Sreenivas Subramoney,Tanay Karnik,Hong Wang,Ian A. Young	5
9	Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling 2016 ·SPIE eBooks ·Lars W. Liebmann,Lawrence T. Pileggi,Kaushik Vaidyanathan	8
10	Systemic optimization of on-chip thermoelectric cooling 2015 ·(unknown),Tanay Karnik,Rahul Khanna,Kelly Lofgreen,(unknown),(unknown),Kaushik Vaidyanathan	3
11	A synthesis methodology for application-specific logic-in-memory designs 2015 ·H. Ekin Sumbul,Kaushik Vaidyanathan,(unknown),Franz Franchetti,Larry Pileggi	4
12	Sub-20 nm design technology co-optimization for standard cell logic 2014 ·International Conference on Computer Aided Design ·Kaushik Vaidyanathan,Lars W. Liebmann,Andrzej J. Strojwas,Larry Pileggi	4
13	Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip 2014 ·Journal of Micro/Nanolithography MEMS and MOEMS ·Kaushik Vaidyanathan,(unknown),Lars W. Liebmann,Kafai Lai,(unknown),Renzhi Liu,Yandong Liu,(unknown),Larry Pileggi	7
14	Building trusted ICs using split fabrication 2014 ·Kaushik Vaidyanathan,Bishnu Prasad Das,(unknown),Renzhi Liu,Larry Pileggi	76
15	Sub-20 nm design technology co-optimization for standard cell logic 2014 ·Kaushik Vaidyanathan,Lars W. Liebmann,Andrzej J. Strojwas,Larry Pileggi	6
16	Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack 2014 ·Kaushik Vaidyanathan,Bishnu Prasad Das,Larry Pileggi	27
17	Rethinking ASIC design with next generation lithography and process integration 2013 ·Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Kaushik Vaidyanathan,Renzhi Liu,Lars W. Liebmann,Kafai Lai,Andrzej J. Strojwas,Larry Pileggi	10
18	<title>Local loops for robust inter-layer routing at sub-20 nm nodes</title> 2012 ·Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Wenbin Huang,Daniel Morris,Neal Lafferty,Lars W. Liebmann,Kaushik Vaidyanathan,Kafai Lai,Larry Pileggi,Andrzej J. Strojwas	4
19	<title>Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node</title> 2012 ·Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Kaushik Vaidyanathan,(unknown),Daniel Morris,Neal Lafferty,Lars W. Liebmann,Mitchell E. Bender,Wenbin Huang,Kafai Lai,Larry Pileggi,Andrzej J. Strojwas	20
20	Design of embedded memory and logic based on pattern constructs 2011 ·Symposium on VLSI Technology ·Daniel Morris,Kaushik Vaidyanathan,Neal Lafferty,Kafai Lai,Lars W. Liebmann,Larry Pileggi	12

About Kaushik Vaidyanathan

Kaushik Vaidyanathan is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Surfaces, Coatings and Films, having authored 26 papers that have together received 320 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (9 papers), Semiconductor materials and devices (9 papers) and Advanced Memory and Neural Computing (8 papers). The work is most often cited by research in Hardware and Architecture (191 citations), Electrical and Electronic Engineering (256 citations) and Cellular and Molecular Neuroscience (49 citations). Kaushik Vaidyanathan has collaborated with scholars based in United States and India. Frequent co-authors include Larry Pileggi, Renzhi Liu, Bishnu Prasad Das, Lars W. Liebmann, Franz Franchetti, Andrzej J. Strojwas, Kafai Lai, Daniel Morris, Tanay Karnik and Neal Lafferty. Their work appears in journals such as Journal of Micro/Nanolithography MEMS and MOEMS, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits and International Conference on Computer Aided Design.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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