James Chien-Mo Li

505 total citations
53 papers, 332 citations indexed

About

James Chien-Mo Li is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Artificial Intelligence. According to data from OpenAlex, James Chien-Mo Li has authored 53 papers receiving a total of 332 indexed citations (citations by other indexed papers that have themselves been cited), including 48 papers in Electrical and Electronic Engineering, 35 papers in Hardware and Architecture and 4 papers in Artificial Intelligence. Recurrent topics in James Chien-Mo Li's work include VLSI and Analog Circuit Testing (34 papers), Integrated Circuits and Semiconductor Failure Analysis (30 papers) and Low-power high-performance VLSI design (14 papers). James Chien-Mo Li is often cited by papers focused on VLSI and Analog Circuit Testing (34 papers), Integrated Circuits and Semiconductor Failure Analysis (30 papers) and Low-power high-performance VLSI design (14 papers). James Chien-Mo Li collaborates with scholars based in Taiwan, United States and Japan. James Chien-Mo Li's co-authors include E.J. McCluskey, Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Yen‐Lung Chen, Chien‐Nan Jimmy Liu, Hung-Yi Hsieh, Chun-Yi Kuo, Yi-Chang Lu and Krishnendu Chakrabarty and has published in prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Circuits and Systems I Regular Papers.

In The Last Decade

James Chien-Mo Li

47 papers receiving 323 citations

Peers

Countries citing papers authored by James Chien-Mo Li

Since Specialization

Citations

This map shows the geographic impact of James Chien-Mo Li's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by James Chien-Mo Li with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites James Chien-Mo Li more than expected).

Fields of papers citing papers by James Chien-Mo Li

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by James Chien-Mo Li. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by James Chien-Mo Li. The network helps show where James Chien-Mo Li may publish in the future.

Co-authorship network of co-authors of James Chien-Mo Li

This figure shows the co-authorship network connecting the top 25 collaborators of James Chien-Mo Li. A scholar is included among the top collaborators of James Chien-Mo Li based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with James Chien-Mo Li. James Chien-Mo Li is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Test Compression for Neuromorphic Chips 2024 ·Xinping Chen, (unknown), (unknown), (unknown), James Chien-Mo Li	1
2	Diagnosis of Quantum Circuits in the NISQ Era 2023 ·Yumin Li, (unknown), (unknown), James Chien-Mo Li	1
3	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning 2021 ·(unknown), (unknown), Chun Chen, (unknown), James Chien-Mo Li, (unknown), (unknown)	6
4	Machine Learning-Based Test Pattern Generation for Neuromorphic Chips 2021 ·(unknown), (unknown), (unknown), James Chien-Mo Li	11
5	Diagnosis technique for Clustered Multiple Transition Delay Faults 2020 ·(unknown), (unknown), (unknown), Po‐Wei Chen, James Chien-Mo Li	3
6	Test methodology for PCHB/PCFB Asynchronous Circuits 2018 ·(unknown), (unknown), (unknown), James Chien-Mo Li, (unknown)	1
7	Physical-aware diagnosis of multiple interconnect defects 2017 ·Po‐Hao Chen, (unknown), Jingyu Chen, Po‐Wei Chen, James Chien-Mo Li	1
8	Test Pattern Compression for Probabilistic Circuits 2017 ·Chih‐Ming Chang, (unknown), James Chien-Mo Li, Hung Chen	3
9	Test Pattern Modification for Average IR-Drop Reduction 2015 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown), Hung-Yi Hsieh, Chengyu Han, James Chien-Mo Li, Xiaoqing Wen	6
10	TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects 2015 ·(unknown), (unknown), (unknown), James Chien-Mo Li	4
11	GPU-based timing-aware test generation for small delay defects 2014 ·(unknown), (unknown), (unknown), James Chien-Mo Li, Michael S. Hsiao, Laung‐Terng Wang	4
12	Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering 2013 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown), (unknown), (unknown), James Chien-Mo Li, (unknown), (unknown), (unknown), (unknown)	7
13	Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits 2013 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Chun-Yi Kuo, (unknown), Yi-Chang Lu, James Chien-Mo Li, Krishnendu Chakrabarty	16
14	Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk 2013 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Ming‐Hong Tsai, (unknown), Hung-Yi Hsieh, James Chien-Mo Li	6
15	Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 2012 ·ACM Transactions on Design Automation of Electronic Systems ·Shianling Wu, Laung‐Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang	3
16	Placement Optimization of Flexible TFT Digital Circuits 2011 ·(unknown), (unknown), (unknown), James Chien-Mo Li	1
17	A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores 2010 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown), James Chien-Mo Li	60
18	Reliability Screening of a-Si TFT Circuits: Very-Low Voltage and ${\rm I}_{\rm DDQ}$ Testing 2010 ·Journal of Display Technology ·(unknown), (unknown), (unknown), I‐Chun Cheng, James Chien-Mo Li	1
19	DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In 2009 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown), (unknown), (unknown), James Chien-Mo Li, Vasco Manquinho	2
20	A Design for Testability Technique for Low Power Delay Fault Testing 2004 ·IEICE Transactions on Electronics ·James Chien-Mo Li	3

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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