D. Moy

699 citations

31 papers · 395 indexed · h-index 11

Hardware and Architecture top 10%
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices 19
- Advancements in Semiconductor Devices and Circuit Design 13
- Integrated Circuits and Semiconductor Failure Analysis 9
- Advancements in Photolithography Techniques 4
- Advanced Memory and Neural Computing 4
- Low-power high-performance VLSI design 4
Atomic and Molecular Physics, and Optics
- Semiconductor materials and interfaces 7
Electronic, Optical and Magnetic Materials
- Copper Interconnects and Reliability 3
Condensed Matter Physics

Co-authors: Yuan Taur B. Davari J.Y.-C. Sun M.R. Wordeman M.R. Polcari T. Kirihata Subramanian S. Iyer C. Y. Wong
Cited by: Hardware and Architecture Electrical and Electronic Engineering Atomic and Molecular Physics, and Optics
Journals: IEEE Electron Device Letters (2 papers)Applied Physics Letters (2 papers)IEEE Transactions on Electron Devices (2 papers)
Partner nations: United States Sweden India

In The Last Decade

D. Moy

29 papers receiving 376 citations

Peers

Countries citing papers authored by D. Moy

Since Specialization

Citations

This map shows the geographic impact of D. Moy's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Moy with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Moy more than expected).

Fields of papers citing papers by D. Moy

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Moy. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Moy. The network helps show where D. Moy may publish in the future.

Co-authorship network

The 25 scholars most cited alongside D. Moy, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with D. Moy Line = papers co-authored together D. Moy links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Self-aligned Fiber Attach on Monolithic Silicon Photonic Chips: Moisture Effect and Hermetic Seal Jingou Yin,Hanife Orhangazi,Giovanni Tatarelli,Patrick Justison,Martin Gall,Tsai-Sheng Kao,Bärbel Metzinger-Schmitz,Yusheng Bian,Thomas Houghton,Anna Agapova,D. Moy,Karen Nummy,吕向洋,Norman Robson,Anika Muthiah,Ken Giewont	2023	0
2	Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies IEEE Electron Device Letters ·Ghorai Prasenjit,Julian‐Almarcegui Cristina,D. Moy,Sj Wright,Jiang Liu,Mille Dahl Andersen,Norman Robson,T. Kirihata,Jason C. S. Woo,Subramanian S. Iyer	2019	12
3	Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond Ghorai Prasenjit,D. Moy,Hiroshi Miya,Morito TAMAKI,Sj Wright,Jiang Liu,Mille Dahl Andersen,Norman Robson,T. Kirihata	2019	6
4	80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity IEEE Journal of Solid-State Circuits ·G Mellier,Татьяна Михайловна Габдурахимова,Amanda Branco e Silva,Chuanying Geng,Ming Yin,John Golz,Michelle Jane Patterson,Randa Khattar,D. Moy,義孝金,Ghorai Prasenjit,T. Kirihata,Subramanian S. Iyer	2018	7
5	80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity Amanda Branco e Silva,Татьяна Михайловна Габдурахимова,G Mellier,Chuanying Geng,浩市村,Ming Yin,John Golz,Michelle Jane Patterson,Randa Khattar,D. Moy,義孝金,Ghorai Prasenjit,T. Kirihata,van den Karin Hurk	2016	10
6	A Compact eFUSE Programmable Array Memory for SOI CMOS John Safran,Roberta Cupido,Julián Andrés España Peña,C. Kothandaraman,Chuanying Geng,Xiang Chen,Keren Wu,Deok‐kee Kim,https://orcid.org/0000-0001-9323-4911,D. Moy,Norman Robson,T. Kirihata,Subramanian S. Iyer	2007	20
7	Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips M. Sailee,John Safran,C. Kothandaraman,Chuanying Geng,Xiang Chen,Keren Wu,Roberta Cupido,D. Moy,T. Kirihata,Subramanian S. Iyer	2007	53
8	Reliability investigation of NiPtSi electrical fuse with different programming mechanisms Sunita,D. Moy,Rajapboyeva Nilufar Raximboyev Musobek Komiljon o`g`li,C. Kothandaraman,John Safran,S. Wu,Norman Robson,Alexander Wäschle	2007	1
9	A high performance 0.25 mu m CMOS technology B. Davari,Wei‐Hsu Chang,M.R. Wordeman,J. De Waele,Yuan Taur,Karen Petrillo,D. Moy,J. J. Bucchignano,Hong Ng,M.G. Rosenfield,أسيل سعيد جبرين الحسنات,Alyssa N. Montalbine	2003	5
10	High performance 0.18 μm SOI CMOS technology E. Leobandung,Martin Dunsmuir,M. Sherony,Helnaria Fermi Pandelisman,R. Schulz,Sonia Valdés Sardiñas,Mukesh Khare,D. K. Sadana,D. Schepis,Niclas Spets,ABULLAH DEMİR,F. White,F. Assaderaghi,D. Moy,Helena Olga Jareb,Jian-Yu Pan,Therese Rosenfeld,B. Davari,G. Shahidi	2003	9
11	A two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM D. Moy,M. Schadt,Chunhua Hu,F. B. Kaufman,A. Ray,Teresa Figueiredo,Mirkamilova Naima Sadiliyevna,D.J. Pearson	2003	0
12	High performance 0.1 μm CMOS devices with 1.5 V power supply Y. Taur,Shalom J. Wind,Y. J. Mii,Y. T. Lii,D. Moy,K.A. Jenkins,Chai Bao-sha,P. Coane,D. Klaus,J. J. Bucchignano,M.G. Rosenfield,M. G. R. Thomson,M.R. Polcari	2002	24
13	The Application of Deep UV Phase Shifted-Single Layer Halftone Reticles to 256 Mbit Dynamic Random Access Memory Cell Patterns Japanese Journal of Applied Physics ·Kohji Hashimoto,Chang Kook Hwang,Yves Coussement,D. Moy,Nursultan Mizamov,Richard A. Ferguson,薫勝田	1994	5
14	A 0.5 &mu;m fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography D. Moy,Jill Mary Gordon,David E. Seeger,J. P. Silverman,Chunhua Hu,F. B. Kaufman,Fang,M. Jaso,Teresa Figueiredo	1990	2
15	Novel self-aligned W/TiN/TiSi2 contact structure for very shallow junctions and interconnections Applied Physics Letters ·(unknown),D. Moy,Stuart K Lee,A. Charaı̈,L. Krusin‐Elbaum,P.J. Restle,Fadhlan Luthfi Chatib Lubis,Young Jacob William Albert	1989	13
16	TiN formed by ion beam nitriding of TiSi2 Journal of Vacuum Science & Technology A Vacuum Surfaces and Films ·Sven Erik Hörnström,D. Moy,A. Charaı̈,J. M. E. Harper,A. Robertsson,Shaofang Gong	1989	3
17	Inverter performance of deep-submicrometer MOSFETs IEEE Electron Device Letters ·G.A. Sai-Halasz,M.R. Wordeman,D. P. Kern,S. A. Rishton,E. Ganin,Hong Ng,D. Moy,T. H. P. Chang,R.H. Dennard	1988	11
18	CMOS 0.5-micron unified digital array using full E-beam lithography R. Johannesson,Linda Napitupulu,P. Coane,D. Moy,F. Troitiño,أسيل سعيد جبرين الحسنات	1987	1
19	Study of contact and shallow junction characteristics in submicron CMOS with self-aligned titanium silicide IBM Journal of Research and Development ·Yuan Taur,B. Davari,D. Moy,J.Y.-C. Sun,C. Y. Ting	1987	7
20	0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography Linda Napitupulu,Y. Taur,D. Moy,R.H. Dennard,Andrey Ishchuk,أسيل سعيد جبرين الحسنات,P. Coane,武志下野,Yenier Torres Izquierdo,Muhammad Ambiya Abid,Sebastian Schnur	1986	9

About D. Moy

D. Moy is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Atomic and Molecular Physics, and Optics, having authored 31 papers that have together received 395 indexed citations. Recurring topics across this work include Semiconductor materials and devices (19 papers), Advancements in Semiconductor Devices and Circuit Design (13 papers), Integrated Circuits and Semiconductor Failure Analysis (9 papers), Semiconductor materials and interfaces (7 papers), Advancements in Photolithography Techniques (4 papers), Advanced Memory and Neural Computing (4 papers), Low-power high-performance VLSI design (4 papers) and Copper Interconnects and Reliability (3 papers). The work is most often cited by research in Hardware and Architecture (47 citations), Electrical and Electronic Engineering (372 citations) and Atomic and Molecular Physics, and Optics (88 citations). D. Moy has collaborated with scholars based in United States, Sweden and India. Frequent co-authors include Yuan Taur, B. Davari, J.Y.-C. Sun, M.R. Wordeman, M.R. Polcari, T. Kirihata, Subramanian S. Iyer, C. Y. Wong, Karen Petrillo and Ching-Fang Hsu. Their work appears in journals such as IEEE Electron Device Letters, Applied Physics Letters, IEEE Transactions on Electron Devices, Japanese Journal of Applied Physics and IEEE Transactions on Device and Materials Reliability.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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