J. Barth

770 total citations
27 papers, 488 citations indexed

About

J. Barth is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, J. Barth has authored 27 papers receiving a total of 488 indexed citations (citations by other indexed papers that have themselves been cited), including 26 papers in Electrical and Electronic Engineering, 12 papers in Hardware and Architecture and 2 papers in Computer Networks and Communications. Recurrent topics in J. Barth's work include Low-power high-performance VLSI design (16 papers), Semiconductor materials and devices (16 papers) and Advancements in Semiconductor Devices and Circuit Design (12 papers). J. Barth is often cited by papers focused on Low-power high-performance VLSI design (16 papers), Semiconductor materials and devices (16 papers) and Advancements in Semiconductor Devices and Circuit Design (12 papers). J. Barth collaborates with scholars based in United States, Germany and Canada. J. Barth's co-authors include Subramanian S. Iyer, P. Parries, T. Kirihata, Erik Nelson, C.H. Stapper, W. Reohr, D. Hoyniak, John Golz, Steven M. Burns and P. Jakobsen and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IBM Journal of Research and Development and 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

In The Last Decade

J. Barth

26 papers receiving 458 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
J. Barth United States	12	437	262	118	27	15	27	488
W.B. Jone United States	12	360 0.8×	361 1.4×	131 1.1×	26 1.0×	27 1.8×	52	455
T. Yoshihara Japan	14	501 1.1×	244 0.9×	157 1.3×	56 2.1×	4 0.3×	43	609
A. Maheshwari United States	9	481 1.1×	170 0.6×	62 0.5×	61 2.3×	3 0.2×	17	509
D. Ayers United States	8	314 0.7×	267 1.0×	147 1.2×	14 0.5×	3 0.2×	13	408
H. Muljono United States	11	353 0.8×	278 1.1×	155 1.3×	23 0.9×	2 0.1×	21	454
P.E. Gronowski United States	9	407 0.9×	272 1.0×	145 1.2×	45 1.7×	3 0.2×	14	503
Georg Georgakos Germany	15	626 1.4×	167 0.6×	34 0.3×	90 3.3×	6 0.4×	48	651
Kunhyuk Kang United States	19	1.2k 2.7×	219 0.8×	40 0.3×	24 0.9×	5 0.3×	32	1.2k
R.P. Preston United States	9	367 0.8×	242 0.9×	127 1.1×	42 1.6×	4 0.3×	13	475
Rei-Fu Huang Taiwan	12	356 0.8×	298 1.1×	91 0.8×	5 0.2×	13 0.9×	28	406

Countries citing papers authored by J. Barth

Since Specialization

Citations

This map shows the geographic impact of J. Barth's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Barth with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Barth more than expected).

Fields of papers citing papers by J. Barth

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Barth. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Barth. The network helps show where J. Barth may publish in the future.

Co-authorship network of co-authors of J. Barth

This figure shows the co-authorship network connecting the top 25 collaborators of J. Barth. A scholar is included among the top collaborators of J. Barth based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J. Barth. J. Barth is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Pilo, Harold, et al.. (2025). A 38Mb/mm² 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology. 498–500.

Zhang, Yanli, R. Krishnan, Sungjae Lee, et al.. (2012). Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. 1–4. 9 indexed citations

Wendel, D., et al.. (2011). IBM POWER7 processor circuit design. IBM Journal of Research and Development. 55(3). 1:1–1:8. 5 indexed citations

Barth, J., et al.. (2010). A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. 342–343. 9 indexed citations

Barth, J., Nianzheng Cao, Erik Nelson, et al.. (2010). A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE Journal of Solid-State Circuits. 46(1). 64–75. 38 indexed citations

Barth, J., W. Reohr, P. Parries, et al.. (2008). A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE Journal of Solid-State Circuits. 43(1). 86–95. 47 indexed citations

Barth, J., W. Reohr, John Golz, et al.. (2008). A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS. 206–207. 4 indexed citations

Barth, J., W. Reohr, P. Parries, et al.. (2007). A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. 486–617. 26 indexed citations

Iyer, Subramanian S., et al.. (2006). Process-design considerations for three dimensional memory integration. Symposium on VLSI Technology. 60–63. 3 indexed citations

10.

Barth, J., et al.. (2005). A 300MHz multi-banked, eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 2. 118–427. 7 indexed citations

11.

Iyer, Subramanian S., et al.. (2005). Embedded DRAM: Technology platform for the Blue Gene/L chip. IBM Journal of Research and Development. 49(2.3). 333–350. 53 indexed citations

12.

Barth, J., et al.. (2005). A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE Journal of Solid-State Circuits. 40(1). 213–222. 21 indexed citations

13.

Pilo, Harold, et al.. (2003). A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE Journal of Solid-State Circuits. 38(11). 1974–1980. 14 indexed citations

14.

Mandelman, J., J. Barth, J. DeBrosse, et al.. (2002). Floating-body concerns for SOI dynamic random access memory (DRAM). 136–137. 5 indexed citations

15.

Barth, J., et al.. (2002). An ASIC library granular DRAM macro with built-in self test. 74–75,. 18 indexed citations

16.

Jakobsen, P., et al.. (2002). Embedded DRAM built in self test and methodology for test insertion. 975–984. 20 indexed citations

17.

Barth, J., et al.. (2002). Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. IBM Journal of Research and Development. 46(6). 675–689. 18 indexed citations

18.

Barth, J., et al.. (1998). Processor-based built-in self-test for embedded DRAM. IEEE Journal of Solid-State Circuits. 33(11). 1731–1740. 69 indexed citations

19.

Barth, J., et al.. (1995). Multipurpose DRAM architecture for optimal power, performance, and product flexibility. IBM Journal of Research and Development. 39(1.2). 51–62. 1 indexed citations

20.

Barth, J., et al.. (1990). A 50 ns 16 Mb DRAM with a 10 ns data rate. 232–233. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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