J. Barth

772 citations

29 papers · 512 · h-index 12

Impact in

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing

Papers in

Electrical and Electronic Engineering 28
- Low-power high-performance VLSI design 16
- Semiconductor materials and devices 16
- Advancements in Semiconductor Devices and Circuit Design 12
- 3D IC and TSV technologies 5
- Integrated Circuits and Semiconductor Failure Analysis 4
- VLSI and FPGA Design Techniques 3
Hardware and Architecture 12
- VLSI and Analog Circuit Testing 9
- Parallel Computing and Optimization Techniques 3

Co-authors: Subramanian S. Iyer (11 shared papers)P. Parries (5 shared papers)T. Kirihata (11 shared papers)Erik Nelson (7 shared papers)C.H. Stapper (3 shared papers)W. Reohr (6 shared papers)D. Hoyniak (1 shared paper)John Golz (6 shared papers)
Journals: IEEE Journal of Solid-State Circuits (6 papers)IBM Journal of Research and Development (4 papers)Journal of Low Power Electronics and Applications (1 paper)Symposium on VLSI Technology (1 paper)2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) (1 paper)
Partner nations: United States Germany Canada

In The Last Decade

J. Barth

28 papers receiving 481 citations

Peers

Countries citing papers authored by J. Barth

Since Specialization

Citations

This map shows the geographic impact of J. Barth's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Barth with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Barth more than expected).

Fields of papers citing papers by J. Barth

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Barth. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Barth. The network helps show where J. Barth may publish in the future.

Co-authors

The 25 scholars most cited alongside J. Barth, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J. Barth Line = papers co-authored together J. Barth links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 29 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC IEEE Journal of Solid-State Circuits ·H.L. Kalter, C.H. Stapper, J. Barth, Jonathan DiLorenzo, C. Drake, J.A. Fifield, G.A. Kelley, Scott C. Lewis, W.B. van der Hoeven, J.A. Yankosky	1990	81
2	Processor-based built-in self-test for embedded DRAM IEEE Journal of Solid-State Circuits ·J. Dreibelbis, J. Barth, H.L. Kalter, R. Kho	1998	69
3	Embedded DRAM: Technology platform for the Blue Gene/L chip IBM Journal of Research and Development ·Subramanian S. Iyer, J. Barth, P. Parries, J. Norum, J. Rice, L. R. Logan, D. Hoyniak	2005	53
4	A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier IEEE Journal of Solid-State Circuits ·J. Barth, W. Reohr, P. Parries, G. Fredeman, John Golz, S.E. Schuster, Richard E. Matick, Hillery C. Hunter, Charles C. Tanner, Joseph Harig, Hoki Kim, (unknown), J. Griesemer, R.P. Havreluk, (unknown), T. Kirihata, Subramanian S. Iyer	2008	48
5	A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache IEEE Journal of Solid-State Circuits ·J. Barth, Kavita Nair, Nianzheng Cao, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, T. Kirihata, W. Reohr	2010	38
6	A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier J. Barth, W. Reohr, P. Parries, G. Fredeman, John Golz, S.E. Schuster, Richard E. Matick, Hillery C. Hunter, Charles C. Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, J. Griesemer, R.P. Havreluk, Kenji YANAGISAWA, T. Kirihata, Subramanian S. Iyer	2007	26
7	A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining IEEE Journal of Solid-State Circuits ·J. Barth, D. Anand, Steven M. Burns, J. Dreibelbis, J.A. Fifield, K. Gorman, M. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale Pontius, Stephen Sliva	2005	21
8	Embedded DRAM built in self test and methodology for test insertion P. Jakobsen, J. Dreibelbis, Gary Pomichter, D. Anand, J. Barth, M. Nelms, Janice Leach, G. Belansek	2002	20
9	An ASIC library granular DRAM macro with built-in self test J. Dreibelbis, J. Barth, R. Kho, T. Kalter	2002	18
10	Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering IBM Journal of Research and Development ·J. Barth, J. Dreibelbis, Erik Nelson, D. Anand, Gary Pomichter, P. Jakobsen, M. Nelms, Janice Leach, G. Belansek	2002	18
11	3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype John Golz, John Safran, Bishan He, Derek Leu, Ming Yin, Todd Weaver, Adis Vehabovic, Yan Sun, Alberto Cestero, Ben Himmel, Gary Maier, C. Kothandaraman, Daniel Fainstein, J. Barth, Norman Robson, T. Kirihata, K. Rim, Subramanian S. Iyer	2011	16
12	A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface IEEE Journal of Solid-State Circuits ·Harold Pilo, D. Anand, J. Barth, Steven M. Burns, Phillip L. Corson, J. Covino, S. Lamphier	2003	14
13	Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology Journal of Low Power Electronics and Applications ·Pooja Batra, Spyridon Skordas, D. LaTulipe, Kevin Winstel, C. Kothandaraman, Ben Himmel, Gary Maier, Bishan He, Deepal Wehella Gamage, John Golz, (unknown), Tuan Vo, Deepika Priyadarshini, Alex Hubbard, Kristian Cauffman, B. Peethala, J. Barth, T. Kirihata, Troy Graves-Abe, Norman Robson, Subramanian S. Iyer	2014	11
14	Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology Pooja Batra, D. LaTulipe, Spyridon Skordas, Kevin Winstel, C. Kothandaraman, Ben Himmel, Gary Maier, Bishan He, Deepal Wehella Gamage, John Golz, (unknown), Tuan Vo, Deepika Priyadarshini, Alex Hubbard, Kristian Cauffman, B. Peethala, J. Barth, T. Kirihata, Troy Graves-Abe, Norman Robson, Subramanian S. Iyer	2013	10
15	Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond Balaji Jayaraman, S.P. Gupta, Yanli Zhang, Puneet Goyal, Herbert L. Ho, R. Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, K. McStay, Bernhard Wunder, J. Barth, Sadanand V. Deshpande, P. Parries, Rajeev Malik, P. Agnello, S. R. Stiffler, Subramanian S. Iyer	2012	9
16	A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache J. Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, W. Reohr, Kavita Nair, Nianzheng Cao	2010	9
17	A 300MHz multi-banked, eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·J. Barth, D. Anand, J. Dreibelbis, Erik Nelson	2005	7
18	A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface H. Pilo, D. Anand, J. Barth, Steven M. Burns, P. Corson, J. Covino, R. Houghton, S. Lamphier	2003	7
19	A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipelining J. Barth, D. Anand, J. Dreibelbis, J. Fifield, K. Gorman, M. Nelms, G. Pomichter, D. Pontius	2004	6
20	IBM POWER7 processor circuit design IBM Journal of Research and Development ·D. Wendel, J. Barth, Daniel Dreps, Shawkat Islam, J. Pille, J. Tierno	2011	5

About J. Barth

J. Barth is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Biomedical Engineering, Computer Networks and Communications and Automotive Engineering, having authored 29 papers that have together received 512 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (16 papers), Semiconductor materials and devices (16 papers), Advancements in Semiconductor Devices and Circuit Design (12 papers), VLSI and Analog Circuit Testing (9 papers), 3D IC and TSV technologies (5 papers), Integrated Circuits and Semiconductor Failure Analysis (4 papers), VLSI and FPGA Design Techniques (3 papers) and Parallel Computing and Optimization Techniques (3 papers). The work is most often cited by research in Hardware and Architecture (262 citations), Electrical and Electronic Engineering (460 citations), Computer Networks and Communications (120 citations), Automotive Engineering (12 citations) and Biomedical Engineering (30 citations). J. Barth has collaborated with scholars based in United States, Germany and Canada. Frequent co-authors include Subramanian S. Iyer, P. Parries, T. Kirihata, Erik Nelson, C.H. Stapper, W. Reohr, D. Hoyniak, John Golz, P. Jakobsen and Hillery C. Hunter. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IBM Journal of Research and Development, Journal of Low Power Electronics and Applications, Symposium on VLSI Technology and 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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