K. Antreich
- Electrical and Electronic Engineering top 5%
- Hardware and Architecture top 0.5%
- Computational Theory and Mathematics top 2%
- Biomedical Engineering
- Artificial Intelligence
- Co-authors
- Helmut GraebFrank JohannesGeorg SiglMichael SchulzKonrad DollBernd WurthUlf SchlichtmannP. Rentrop
- Topics
- VLSI and Analog Circuit Testing (34 papers)VLSI and FPGA Design Techniques (27 papers)Low-power high-performance VLSI design (22 papers)
- Cited by
- Hardware and ArchitectureElectrical and Electronic EngineeringComputational Theory and Mathematics
In The Last Decade
K. Antreich
45 papers receiving 1.4k citations
Peers
Comparison fields: 5 of 55
- Electrical and Electronic Engineering 1.4k
- Hardware and Architecture 1.1k
- Computational Theory and Mathematics 233
- Biomedical Engineering 90
- Artificial Intelligence 88
Countries citing papers authored by K. Antreich
This map shows the geographic impact of K. Antreich's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Antreich with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Antreich more than expected).
Fields of papers citing papers by K. Antreich
This network shows the impact of papers produced by K. Antreich. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Antreich. The network helps show where K. Antreich may publish in the future.
Co-authorship network of co-authors of K. Antreich
This figure shows the co-authorship network connecting the top 25 collaborators of K. Antreich. A scholar is included among the top collaborators of K. Antreich based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Antreich. K. Antreich is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 4 | |
| 2 | 3 | |
| 3 | 1 | |
| 4 | 20 | |
| 5 | 12 | |
| 6 | 1 | |
| 7 | 11 | |
| 8 | 10 | |
| 9 | 40 | |
| 10 | 20 | |
| 11 | 34 | |
| 12 | 13 | |
| 13 | 37 | |
| 14 | 13 | |
| 15 | 12 | |
| 16 | 153 | |
| 17 | 400 | |
| 18 | 102 | |
| 19 | 6 | |
| 20 | On the interactive optimization of electrical circuits | 1 |
About K. Antreich
K. Antreich is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computational Theory and Mathematics, having authored 45 papers that have together received 1.6k indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (34 papers), VLSI and FPGA Design Techniques (27 papers) and Low-power high-performance VLSI design (22 papers). The work is most often cited by research in Hardware and Architecture (1.1k citations), Electrical and Electronic Engineering (1.4k citations) and Computational Theory and Mathematics (233 citations). K. Antreich has collaborated with scholars based in Germany and Canada. Frequent co-authors include Helmut Graeb, Frank Johannes, Georg Sigl, Michael Schulz, Konrad Doll, Bernd Wurth, Ulf Schlichtmann, P. Rentrop, Roland Bulirsch and Peter Schneider. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Circuits and Systems and ACM Transactions on Design Automation of Electronic Systems.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.