Shianling Wu

442 total citations
23 papers, 313 citations indexed

About

Shianling Wu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, Shianling Wu has authored 23 papers receiving a total of 313 indexed citations (citations by other indexed papers that have themselves been cited), including 21 papers in Electrical and Electronic Engineering, 20 papers in Hardware and Architecture and 9 papers in Control and Systems Engineering. Recurrent topics in Shianling Wu's work include Integrated Circuits and Semiconductor Failure Analysis (20 papers), VLSI and Analog Circuit Testing (20 papers) and Engineering and Test Systems (9 papers). Shianling Wu is often cited by papers focused on Integrated Circuits and Semiconductor Failure Analysis (20 papers), VLSI and Analog Circuit Testing (20 papers) and Engineering and Test Systems (9 papers). Shianling Wu collaborates with scholars based in United States, Japan and Taiwan. Shianling Wu's co-authors include Xiaoqing Wen, Vishwani D. Agrawal, Laung‐Terng Wang, Y. Zorian, Sen‐Wei Tsai, Hiroshi Furukawa, Chih‐Jen Lin, Zhigang Jiang, Zhigang Wang and Xinli Gu and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM Transactions on Design Automation of Electronic Systems and IEEE Design & Test of Computers.

In The Last Decade

Shianling Wu

23 papers receiving 287 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Shianling Wu United States	8	303	299	53	12	12	23	313
Rubin Parekhji India	12	293 1.0×	312 1.0×	33 0.6×	8 0.7×	19 1.6×	65	332
Wangqi Qiu United States	9	362 1.2×	383 1.3×	19 0.4×	7 0.6×	14 1.2×	16	395
E. Volkerink United States	10	390 1.3×	381 1.3×	70 1.3×	4 0.3×	18 1.5×	12	402
A.S.M. Hassan Canada	5	309 1.0×	320 1.1×	40 0.8×	6 0.5×	9 0.8×	6	340
Urban Ingelsson Sweden	10	285 0.9×	276 0.9×	43 0.8×	6 0.5×	8 0.7×	25	307
G. Hetherington United States	6	451 1.5×	447 1.5×	65 1.2×	4 0.3×	8 0.7×	8	466
Vivek Chickermane United States	15	573 1.9×	597 2.0×	50 0.9×	6 0.5×	19 1.6×	43	623
W. Needham United States	7	326 1.1×	355 1.2×	30 0.6×	4 0.3×	10 0.8×	9	371
Emil Gizdarski United States	9	345 1.1×	343 1.1×	63 1.2×	9 0.8×	15 1.3×	24	356
T.J. Snethen United States	7	406 1.3×	397 1.3×	78 1.5×	8 0.7×	21 1.8×	11	411

Countries citing papers authored by Shianling Wu

Since Specialization

Citations

This map shows the geographic impact of Shianling Wu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Shianling Wu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Shianling Wu more than expected).

Fields of papers citing papers by Shianling Wu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Shianling Wu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Shianling Wu. The network helps show where Shianling Wu may publish in the future.

Co-authorship network of co-authors of Shianling Wu

This figure shows the co-authorship network connecting the top 25 collaborators of Shianling Wu. A scholar is included among the top collaborators of Shianling Wu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Shianling Wu. Shianling Wu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Wu, Shianling, Laung‐Terng Wang, Xiaoqing Wen, et al.. (2012). Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Transactions on Design Automation of Electronic Systems. 17(4). 1–16. 3 indexed citations

Wang, Laung‐Terng, et al.. (2010). Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29(2). 299–312. 8 indexed citations

Hung, Jeffrey, et al.. (2010). Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. 331–339. 2 indexed citations

Wang, Laung‐Terng, Nur A. Touba, Zhigang Jiang, et al.. (2010). CSER: BISER-based concurrent soft-error resilience. 8. 153–158. 1 indexed citations

Wu, Shianling, Laung‐Terng Wang, Hiroshi Furukawa, et al.. (2010). Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. 358–366. 7 indexed citations

Wang, Laung‐Terng, Shianling Wu, Kuen-Jong Lee, et al.. (2009). Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Design & Test of Computers. 26(1). 26–35. 3 indexed citations

Jone, Wen-Ben, et al.. (2009). Analysis of Resistive Bridging Defects in a Synchronizer. 443–449. 2 indexed citations

Qian, Jun, Xingang Wang, Xiangfeng Li, et al.. (2009). Logic BIST Architecture for System-Level Test and Diagnosis. 21–26. 6 indexed citations

Wang, Laung‐Terng, Shianling Wu, Kuen-Jong Lee, et al.. (2008). Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. 1–9. 5 indexed citations

10.

Wu, Shianling, et al.. (2008). Practical Challenges in Logic BIST Implementation  Case Studies. 265–265. 1 indexed citations

11.

Wang, Laung‐Terng, Xiaoqing Wen, Shianling Wu, et al.. (2008). VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Design & Test of Computers. 25(2). 122–130. 29 indexed citations

12.

Wu, Shianling, Laung‐Terng Wang, Zhigang Jiang, et al.. (2008). On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. 143–151. 1 indexed citations

13.

Wu, Shianling, et al.. (2006). Test compression and logic BIST at your fingertips. 1284–1285. 1 indexed citations

14.

Wang, Laung‐Terng, et al.. (2006). Ultrascan: using time-division demultiplexing/multiplexing (TDDM/TDM) with virtualscan for test cost reduction. 18. 946–953. 13 indexed citations

15.

Wen, Xiaoqing, et al.. (2006). At-speed logic BIST architecture for multi-clock designs. 475–478. 13 indexed citations

16.

Agrawal, Vishwani D., et al.. (2002). A non-enumerative path delay fault simulator for sequential circuits. 934–943. 6 indexed citations

17.

Butler, Kenneth M., et al.. (1998). Relative Effectiveness Of Tests. IEEE Design & Test of Computers. 15(1). 83–90. 4 indexed citations

18.

Agrawal, Vishwani D., et al.. (1994). Built-in Self-Test for Digital Integrated Circuits. AT&T Technical Journal. 73(2). 30–39. 46 indexed citations

19.

Davidson, Scott, et al.. (1994). Trends in Digital Device Test Methodologies. AT&T Technical Journal. 73(2). 10–18. 2 indexed citations

20.

Wu, Shianling, et al.. (1985). A Sequential Circuit Test Generation System.. International Test Conference. 57–61. 67 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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