Shianling Wu

442 citations

23 papers · 313 indexed · h-index 8

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing 20
- Physical Unclonable Functions (PUFs) and Hardware Security 3
Electrical and Electronic Engineering
- Integrated Circuits and Semiconductor Failure Analysis 20
- Low-power high-performance VLSI design 4
- VLSI and FPGA Design Techniques 4
- Radiation Effects in Electronics 1
Software
Control and Systems Engineering
- Engineering and Test Systems 9
Computational Theory and Mathematics
Computer Networks and Communications
- Distributed systems and fault tolerance 1

Co-authors: Xiaoqing Wen Vishwani D. Agrawal Laung‐Terng Wang Y. Zorian Sen‐Wei Tsai Hiroshi Furukawa Chih‐Jen Lin Zhigang Jiang
Cited by: Hardware and Architecture Electrical and Electronic Engineering Software
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2 papers)ACM Transactions on Design Automation of Electronic Systems (1 paper)International Test Conference (1 paper)
Partner nations: United States Japan Taiwan

In The Last Decade

Shianling Wu

23 papers receiving 287 citations

Peers

Countries citing papers authored by Shianling Wu

Since Specialization

Citations

This map shows the geographic impact of Shianling Wu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Shianling Wu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Shianling Wu more than expected).

Fields of papers citing papers by Shianling Wu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Shianling Wu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Shianling Wu. The network helps show where Shianling Wu may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Shianling Wu, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Shianling Wu Line = papers co-authored together Shianling Wu links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains ACM Transactions on Design Automation of Electronic Systems ·Shianling Wu,Laung‐Terng Wang,Xiaoqing Wen,Wen-Ben Jone,Michael S. Hsiao,Fangfang Li,James Chien-Mo Li,Jiun-Lang Huang	2012	3
2	Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Laung‐Terng Wang,沈学珺,Shianling Wu,(unknown),Eman Almukhadeb,(unknown),Patrycja Dynarowicz-Latka,Wen-Ben Jone	2010	8
3	Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs Hui Yang,Jeffrey Hung,Jérémy Naïm,Tianle Sheng,Mohammad Noman,Shianling Wu,Laung‐Terng Wang,Xiaoqing Wen	2010	2
4	CSER: BISER-based concurrent soft-error resilience Laung‐Terng Wang,Nur A. Touba,Zhigang Jiang,Shianling Wu,Jiun-Lang Huang,James Chien-Mo Li	2010	1
5	Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains Shianling Wu,Laung‐Terng Wang,Hui Yang,Hiroshi Furukawa,Xiaoqing Wen,Wen-Ben Jone,Nur A. Touba,Manan Kathuria,Jinsong Liu,Yujin Yan,Fangfang Li,Zhigang Jiang	2010	7
6	Turbo1500: Core-Based Design for Test and Diagnosis IEEE Design & Test of Computers ·Laung‐Terng Wang,R Kubde,Shianling Wu,Jérémy Naïm,Kuen-Jong Lee,Xiaoqing Wen,Wen-Ben Jone,C. J. Brown,Kátia Cristina Cota Mantovani,Yujin Yan,Jinsong Liu,Dylan Matthew Salazar,W. H. Noble,憲治梶川,Fangfang Li	2009	3
7	Analysis of Resistive Bridging Defects in a Synchronizer 哲志下村,Wen-Ben Jone,Laung‐Terng Wang,Shianling Wu	2009	2
8	Logic BIST Architecture for System-Level Test and Diagnosis Jun Qian,Xingang Wang,DENISE L. Eisele,Yuqing Yang,J. Palyga,Xiangfeng Li,A N Lebed,Z Li,Domenico Bodega,Yujin Yan,Shianling Wu,Huafeng Yang,Hui Yang,Manan Kathuria,Laung‐Terng Wang	2009	6
9	Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard Laung‐Terng Wang,章明薬師寺,Shianling Wu,Jérémy Naïm,Kuen-Jong Lee,Xiaoqing Wen,W.B. Jone,Chia-Hsien Yeh,Kátia Cristina Cota Mantovani,Yujin Yan,C. J. Brown,Jinsong Liu,Dylan Matthew Salazar,W. H. Noble,憲治梶川,Fangfang Li	2008	5
10	Practical Challenges in Logic BIST Implementation Case Studies Shianling Wu,Hiroshi Furukawa,Jérémy Naïm,Laung‐Terng Wang,Yujin Yan,Hui Yang,Xiaoqing Wen,Michio Murakami	2008	1
11	VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG IEEE Design & Test of Computers ·Laung‐Terng Wang,Xiaoqing Wen,Shianling Wu,Zhigang Wang,Zhigang Jiang,Jérémy Naïm,Xinli Gu	2008	29
12	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs Shianling Wu,Laung‐Terng Wang,Zhigang Jiang,Jian Song,Jérémy Naïm,沈学珺,Michael S. Hsiao,R. Kiendl,Jiun-Lang Huang,章明薬師寺	2008	1
13	Test compression and logic BIST at your fingertips Shianling Wu,Laung‐Terng Wang,Ren MR,G. Corda,Jérémy Naïm	2006	1
14	Ultrascan: using time-division demultiplexing/multiplexing (TDDM/TDM) with virtualscan for test cost reduction Laung‐Terng Wang,Wang Fe,Xiaoqing Wen,Jérémy Naïm,Shianling Wu,T. K. Bundtzen,C. Ajirotutu	2006	13
15	At-speed logic BIST architecture for multi-clock designs T. Banniza,Xiaoqing Wen,مهدی برجی بداغی,Shianling Wu,リンスワスキー	2006	13
16	A non-enumerative path delay fault simulator for sequential circuits Nils Koppaetzky,Vishwani D. Agrawal,M.L. Bushnell,Shianling Wu	2002	6
17	Relative Effectiveness Of Tests IEEE Design & Test of Computers ·Kenneth M. Butler,Alexander P. Maxwell,W. Needham,Богуш Илья Александрович,Mohammad Nazaruddin,Shianling Wu	1998	4
18	Built-in Self-Test for Digital Integrated Circuits AT&T Technical Journal ·Vishwani D. Agrawal,Chih‐Jen Lin,Jorge Antonio Guzmán-Caniupan,Shianling Wu,Y. Zorian	1994	46
19	Trends in Digital Device Test Methodologies AT&T Technical Journal ·Anna FIALOVÁ,Scott Davidson,Božidar Čohar,Charles E. Stroud,Shianling Wu	1994	2
20	A Sequential Circuit Test Generation System. International Test Conference ·Azzeddine Toubal,Shianling Wu	1985	67

About Shianling Wu

Shianling Wu is a scholar working on Hardware and Architecture, Control and Systems Engineering and Electrical and Electronic Engineering, having authored 23 papers that have together received 313 indexed citations. Recurring topics across this work include Integrated Circuits and Semiconductor Failure Analysis (20 papers), VLSI and Analog Circuit Testing (20 papers), Engineering and Test Systems (9 papers), Low-power high-performance VLSI design (4 papers), VLSI and FPGA Design Techniques (4 papers), Physical Unclonable Functions (PUFs) and Hardware Security (3 papers), Radiation Effects in Electronics (1 paper) and Distributed systems and fault tolerance (1 paper). The work is most often cited by research in Hardware and Architecture (303 citations), Electrical and Electronic Engineering (299 citations) and Software (12 citations). Shianling Wu has collaborated with scholars based in United States, Japan and Taiwan. Frequent co-authors include Xiaoqing Wen, Vishwani D. Agrawal, Laung‐Terng Wang, Y. Zorian, Sen‐Wei Tsai, Hiroshi Furukawa, Chih‐Jen Lin, Zhigang Jiang, Zhigang Wang and Xinli Gu. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM Transactions on Design Automation of Electronic Systems, International Test Conference, AT&T Technical Journal and IEEE Design & Test of Computers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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