Shianling Wu
- Hardware and Architecture top 2%
- Electrical and Electronic Engineering
- Control and Systems Engineering
- Computational Theory and Mathematics
- Software
- Co-authors
- Xiaoqing WenVishwani D. AgrawalLaung‐Terng WangY. ZorianSen‐Wei TsaiHiroshi FurukawaChih‐Jen LinZhigang Jiang
- Topics
- Integrated Circuits and Semiconductor Failure Analysis (20 papers)VLSI and Analog Circuit Testing (20 papers)Engineering and Test Systems (9 papers)
- Journals
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsACM Transactions on Design Automation of Electronic SystemsIEEE Design & Test of Computers
- Partner nations
- United StatesJapanTaiwan
In The Last Decade
Shianling Wu
23 papers receiving 287 citations
Peers
Comparison fields: 5 of 11
- Hardware and Architecture 303
- Electrical and Electronic Engineering 299
- Control and Systems Engineering 53
- Computational Theory and Mathematics 12
- Software 12
Countries citing papers authored by Shianling Wu
This map shows the geographic impact of Shianling Wu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Shianling Wu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Shianling Wu more than expected).
Fields of papers citing papers by Shianling Wu
This network shows the impact of papers produced by Shianling Wu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Shianling Wu. The network helps show where Shianling Wu may publish in the future.
Co-authorship network of co-authors of Shianling Wu
This figure shows the co-authorship network connecting the top 25 collaborators of Shianling Wu. A scholar is included among the top collaborators of Shianling Wu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Shianling Wu. Shianling Wu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 3 | |
| 2 | 8 | |
| 3 | 2 | |
| 4 | 1 | |
| 5 | 7 | |
| 6 | 3 | |
| 7 | 2 | |
| 8 | 6 | |
| 9 | 5 | |
| 10 | 1 | |
| 11 | 29 | |
| 12 | 1 | |
| 13 | 1 | |
| 14 | 13 | |
| 15 | 13 | |
| 16 | 6 | |
| 17 | 4 | |
| 18 | 46 | |
| 19 | 2 | |
| 20 | A Sequential Circuit Test Generation System. | 67 |
About Shianling Wu
Shianling Wu is a scholar working on Hardware and Architecture, Control and Systems Engineering and Electrical and Electronic Engineering, having authored 23 papers that have together received 313 indexed citations. Recurring topics across this work include Integrated Circuits and Semiconductor Failure Analysis (20 papers), VLSI and Analog Circuit Testing (20 papers) and Engineering and Test Systems (9 papers). The work is most often cited by research in Hardware and Architecture (303 citations), Electrical and Electronic Engineering (299 citations) and Software (12 citations). Shianling Wu has collaborated with scholars based in United States, Japan and Taiwan. Frequent co-authors include Xiaoqing Wen, Vishwani D. Agrawal, Laung‐Terng Wang, Y. Zorian, Sen‐Wei Tsai, Hiroshi Furukawa, Chih‐Jen Lin, Zhigang Jiang, Zhigang Wang and Xinli Gu. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM Transactions on Design Automation of Electronic Systems and IEEE Design & Test of Computers.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.