Vishwani D. Agrawal

10.8k total citations · 1 hit paper
375 papers, 7.4k citations indexed

About

Vishwani D. Agrawal is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, Vishwani D. Agrawal has authored 375 papers receiving a total of 7.4k indexed citations (citations by other indexed papers that have themselves been cited), including 336 papers in Electrical and Electronic Engineering, 310 papers in Hardware and Architecture and 26 papers in Control and Systems Engineering. Recurrent topics in Vishwani D. Agrawal's work include VLSI and Analog Circuit Testing (294 papers), Integrated Circuits and Semiconductor Failure Analysis (227 papers) and Low-power high-performance VLSI design (125 papers). Vishwani D. Agrawal is often cited by papers focused on VLSI and Analog Circuit Testing (294 papers), Integrated Circuits and Semiconductor Failure Analysis (227 papers) and Low-power high-performance VLSI design (125 papers). Vishwani D. Agrawal collaborates with scholars based in United States, India and Germany. Vishwani D. Agrawal's co-authors include M.L. Bushnell, Kwang‐Ting Cheng, Srimat Chakradhar, Kewal K. Saluja, Sharad Seth, Rahul Agrawal, Sunil Jain, C.R. Kime, Fan Wang and T.J. Chakraborty and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Antennas and Propagation.

In The Last Decade

Vishwani D. Agrawal

357 papers receiving 6.9k citations

Hit Papers

Essentials of Electronic Testing for Digital, Memory and ... 2002 2026 2010 2018 2002 250 500 750 1000
What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

  1. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
    2002 1.0k citations M.L. Bushnell, Vishwani D. Agrawal profile →

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Vishwani D. Agrawal United States 40 6.5k 6.3k 624 442 355 375 7.4k
M. Sonza Reorda Italy 38 5.5k 0.8× 5.3k 0.8× 521 0.8× 1.2k 2.8× 346 1.0× 543 6.5k
A. Richard Newton United States 35 3.8k 0.6× 3.1k 0.5× 194 0.3× 238 0.5× 834 2.3× 147 5.6k
Israel Koren United States 33 2.4k 0.4× 2.4k 0.4× 155 0.2× 85 0.2× 329 0.9× 262 4.4k
Dhiraj K. Pradhan United States 35 3.1k 0.5× 2.5k 0.4× 269 0.4× 275 0.6× 536 1.5× 290 4.8k
S.M. Reddy United States 48 9.6k 1.5× 9.7k 1.5× 1.0k 1.6× 661 1.5× 440 1.2× 598 10.6k
M. Violante Italy 32 2.8k 0.4× 2.5k 0.4× 168 0.3× 431 1.0× 86 0.2× 222 3.3k
Luca P. Carloni United States 35 3.2k 0.5× 2.3k 0.4× 109 0.2× 129 0.3× 357 1.0× 206 5.2k
Michael Wirthlin United States 33 2.7k 0.4× 2.4k 0.4× 105 0.2× 142 0.3× 111 0.3× 145 3.4k
Farid N. Najm Canada 35 5.1k 0.8× 3.3k 0.5× 145 0.2× 45 0.1× 412 1.2× 206 5.6k
Alex Orailoğlu United States 26 2.2k 0.3× 2.3k 0.4× 286 0.5× 83 0.2× 136 0.4× 274 2.7k

Countries citing papers authored by Vishwani D. Agrawal

Since Specialization
Citations

This map shows the geographic impact of Vishwani D. Agrawal's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Vishwani D. Agrawal with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Vishwani D. Agrawal more than expected).

Fields of papers citing papers by Vishwani D. Agrawal

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Vishwani D. Agrawal. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Vishwani D. Agrawal. The network helps show where Vishwani D. Agrawal may publish in the future.

Co-authorship network of co-authors of Vishwani D. Agrawal

This figure shows the co-authorship network connecting the top 25 collaborators of Vishwani D. Agrawal. A scholar is included among the top collaborators of Vishwani D. Agrawal based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Vishwani D. Agrawal. Vishwani D. Agrawal is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Agrawal, Vishwani D., et al.. (2021). Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. 316–321. 21 indexed citations
2.
Agrawal, Vishwani D., et al.. (2010). Soft error considerations for computer web servers. 269–274. 6 indexed citations
3.
Larsson, Erik, et al.. (2009). On Minimization of Peak Power during SoC Test. NOT FOUND REPOSITORY (Indian Institute of Science Bangalore). 1 indexed citations
4.
Agrawal, Vishwani D., et al.. (2006). Spectral RTL Test Generation for Gate-Level Stuck-at Faults. 83–88. 11 indexed citations
5.
Saluja, Kewal K., et al.. (2002). Multiple Faults: Modeling, Simulation and Test. Asia and South Pacific Design Automation Conference. 592–597. 16 indexed citations
6.
Agrawal, Vishwani D., et al.. (1998). Tutorial: Delay Fault Models and Coverage. 364–369. 20 indexed citations
7.
Heragu, K., J.H. Patel, & Vishwani D. Agrawal. (1997). Fast identification of untestable delay faults using implications. International Conference on Computer Aided Design. 642–647. 46 indexed citations
8.
Heragu, K., J.H. Patel, & Vishwani D. Agrawal. (1996). SIGMA: a simulator for segment delay faults. International Conference on Computer Aided Design. 502–508. 8 indexed citations
9.
Chakraborty, T.J., Vishwani D. Agrawal, & M.L. Bushnell. (1992). Delay fault models and test generation for random logic sequential circuits. Design Automation Conference. 165–172. 77 indexed citations
10.
Chakradhar, Srimat, et al.. (1992). Finite state machine synthesis with fault tolerant test function. Design Automation Conference. 562–567. 2 indexed citations
11.
Agrawal, Prathima, Vishwani D. Agrawal, & Sharad Seth. (1992). DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits. European Design Automation Conference. 138–141. 5 indexed citations
12.
Agrawal, Vishwani D. & Srimat Chakradhar. (1990). Performance estimation in a massively parallel system. Conference on High Performance Computing (Supercomputing). 306–313. 6 indexed citations
13.
Agrawal, Vishwani D. & Sharad Seth. (1988). Tutorial test generation for VLSI chips. 19 indexed citations
14.
Agrawal, Vishwani D., Kwang‐Ting Cheng, & Prathima Agrawal. (1988). CONTEST: a concurrent test generator for sequential circuits. Design Automation Conference. 84–89. 57 indexed citations
15.
Jain, Sunil & Vishwani D. Agrawal. (1984). STAFAN: An Alternative to Fault Simulation. Design Automation Conference. 475–480. 58 indexed citations
16.
Dunlop, A.E., et al.. (1984). Chip Layout Optimization Using Critical Path Weighting. Design Automation Conference. 278–281. 122 indexed citations
17.
Agrawal, Vishwani D.. (1984). Will testability analysis replace fault simulation. International Test Conference. 111(1). 718–718. 1 indexed citations
18.
Agrawal, Vishwani D. & M.R. Mercer. (1982). Testability Measures : What Do They Tell Us ?. International Test Conference. 391–399. 46 indexed citations
19.
Agrawal, Vishwani D.. (1982). Synchronous Path Analysis in MOS Circuit Simulator. Design Automation Conference. 629–635. 35 indexed citations
20.
Mercer, M.R., et al.. (1981). Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation.. International Test Conference. 561–565. 5 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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