T.J. Snethen

508 total citations
11 papers, 411 citations indexed

About

T.J. Snethen is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering. According to data from OpenAlex, T.J. Snethen has authored 11 papers receiving a total of 411 indexed citations (citations by other indexed papers that have themselves been cited), including 10 papers in Hardware and Architecture, 10 papers in Electrical and Electronic Engineering and 3 papers in Control and Systems Engineering. Recurrent topics in T.J. Snethen's work include VLSI and Analog Circuit Testing (10 papers), Integrated Circuits and Semiconductor Failure Analysis (8 papers) and VLSI and FPGA Design Techniques (4 papers). T.J. Snethen is often cited by papers focused on VLSI and Analog Circuit Testing (10 papers), Integrated Circuits and Semiconductor Failure Analysis (8 papers) and VLSI and FPGA Design Techniques (4 papers). T.J. Snethen collaborates with scholars based in United States and India. T.J. Snethen's co-authors include Brion Keller, C. Barnhart, B. Koenemann, S. Patil, R. Kapur, T.W. Williams, Bryan Robbins, Peilin Song, W. Huott and B. E. Foutz and has published in prestigious journals such as IBM Journal of Research and Development, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Design Automation Conference.

In The Last Decade

T.J. Snethen

11 papers receiving 377 citations

Peers

T.J. Snethen
I. Hartanto United States
E. Volkerink United States
P. Wohl United States
P. Franco United States
Andre Hertwig Germany
P.G. Ryan United States
D.B.I. Feltham United States
K.D. Wagner United States
G. Hetherington United States
T.J. Chakraborty United States
I. Hartanto United States
T.J. Snethen
Citations per year, relative to T.J. Snethen T.J. Snethen (= 1×) peers I. Hartanto

Countries citing papers authored by T.J. Snethen

Since Specialization
Citations

This map shows the geographic impact of T.J. Snethen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by T.J. Snethen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites T.J. Snethen more than expected).

Fields of papers citing papers by T.J. Snethen

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by T.J. Snethen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by T.J. Snethen. The network helps show where T.J. Snethen may publish in the future.

Co-authorship network of co-authors of T.J. Snethen

This figure shows the co-authorship network connecting the top 25 collaborators of T.J. Snethen. A scholar is included among the top collaborators of T.J. Snethen based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with T.J. Snethen. T.J. Snethen is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

11 of 11 papers shown
1.
Keller, Brion, B. E. Foutz, Vivek Chickermane, et al.. (2014). Efficient testing of hierarchical core-based SOCs. 1–10. 11 indexed citations
2.
3.
Chen, Xinghao, et al.. (2003). A simplified method for testing the IBM pipeline partial-scan microprocessor. 13. 321–326. 2 indexed citations
4.
Koenemann, B., et al.. (2002). A SmartBIST variant with guaranteed encoding. 325–330. 224 indexed citations
5.
Kapur, R., S. Patil, T.J. Snethen, & T.W. Williams. (2002). Design of an efficient weighted random pattern generation system. 491–500. 38 indexed citations
6.
Robbins, Bryan, et al.. (2002). Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. 717–726. 23 indexed citations
7.
Kapur, R., S. Patil, T.J. Snethen, & T.W. Williams. (1996). A weighted random pattern test generation system. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 15(8). 1020–1025. 30 indexed citations
8.
Hartmann, C., et al.. (1991). Algorithm for generating optimal tests for exclusive-or networks. IEE Proceedings E Computers and Digital Techniques. 138(2). 93–93. 4 indexed citations
9.
Keller, Brion & T.J. Snethen. (1990). Built-in self-test support in the IBM Engineering Design System. IBM Journal of Research and Development. 34(2.3). 406–415. 38 indexed citations
10.
Snethen, T.J.. (1977). Simulator-oriented fault test generator. Design Automation Conference. 342–347. 34 indexed citations
11.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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2026