Wen-Ben Jone

1.1k citations

73 papers · 825 indexed · h-index 14

Impact in

Hardware and Architecture top 1%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
Computer Networks and Communications top 5%
- Interconnection Networks and Systems

Papers in

Hardware and Architecture 58
- VLSI and Analog Circuit Testing 48
- Parallel Computing and Optimization Techniques 11
- Embedded Systems Design Techniques 6
Software 6

Co-authors: Qing-An Zeng Ming Li Ranga Vemuri S.R. Das Xingguo Xiong Mansour H. Assaf Emil M. Petriu Yu‐Liang Wu
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (9 papers)IEEE Transactions on Instrumentation and Measurement (6 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (4 papers)ACM Transactions on Design Automation of Electronic Systems (2 papers)IEEE Transactions on Reliability (1 paper)
Partner nations: United States Taiwan Canada

In The Last Decade

Wen-Ben Jone

70 papers receiving 776 citations

Peers

Countries citing papers authored by Wen-Ben Jone

Since Specialization

Citations

This map shows the geographic impact of Wen-Ben Jone's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Wen-Ben Jone with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Wen-Ben Jone more than expected).

Fields of papers citing papers by Wen-Ben Jone

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Wen-Ben Jone. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Wen-Ben Jone. The network helps show where Wen-Ben Jone may publish in the future.

Co-authors

The 25 scholars most cited alongside Wen-Ben Jone, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Wen-Ben Jone Line = papers co-authored together Wen-Ben Jone links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Path delay testing in resilient system Qiang Han, C. J. Brown, Wen-Ben Jone, Qiang Xu	2013	5
2	A cross-layer fault-tolerant design method for high manufacturing yield and system reliability C. J. Brown, Qiang Han, Wen-Ben Jone, Yu‐Liang Wu	2013	1
3	Testing of Synchronizers in Asynchronous FIFO Journal of Electronic Testing ·哲志下村, Laung‐Terng Wang, Yu‐Liang Wu, Wen-Ben Jone	2013	5
4	A configurable bus-tracer for error reproduction in post-silicon validation Garry D. Willett, K.G. Duleep, Wen-Ben Jone, Tien-Fu Chen	2013	2
5	On testing timing-speculative circuits Feng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu	2013	5
6	Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains ACM Transactions on Design Automation of Electronic Systems ·Shianling Wu, Laung‐Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang	2012	3
7	Stretching the limit of microarchitectural level leakage control with adaptive light-weight Vth hopping International Conference on Computer Aided Design ·Yiming Qu, Wen-Ben Jone, Ranga Vemuri	2010	3
8	Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs International Conference on Computer Aided Design ·Yiming Qu, Ranga Vemuri, Wen-Ben Jone	2010	1
9	Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Laung‐Terng Wang, 沈学珺, Shianling Wu, (unknown), Eman Almukhadeb, (unknown), Patrycja Dynarowicz-Latka, Wen-Ben Jone	2010	8
10	Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer Journal of Electronic Testing ·哲志下村, Wen-Ben Jone, Laung‐Terng Wang	2010	1
11	Turbo1500: Core-Based Design for Test and Diagnosis IEEE Design & Test of Computers ·Laung‐Terng Wang, R Kubde, Shianling Wu, Jérémy Naïm, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, C. J. Brown, Kátia Cristina Cota Mantovani, Yujin Yan, Jinsong Liu, Dylan Matthew Salazar, W. H. Noble, 憲治梶川, Fangfang Li	2009	3
12	Analysis of Resistive Bridging Defects in a Synchronizer 哲志下村, Wen-Ben Jone, Laung‐Terng Wang, Shianling Wu	2009	2
13	Accurate energy breakeven time estimation for run-time power gating International Conference on Computer Aided Design ·Yiming Qu, Wen-Ben Jone, Ranga Vemuri	2008	7
14	Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach IEEE Transactions on Instrumentation and Measurement ·I.O. Dmytryk, E. V. Pluchevskaya, Satyendra N. Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Şahinoglu	2007	41
15	Design and analysis of self-repairable MEMS accelerometer Xingguo Xiong, Malcolm Mcisaac, Wen-Ben Jone	2006	13
16	Testing Analog and Mixed-Signal Circuits with Built-In Hardware - A New Approach 2005 IEEE Instrumentationand Measurement Technology Conference Proceedings ·E. V. Pluchevskaya, Mansour H. Assaf, Emil M. Petriu, Mehmet Şahinoglu, Wen-Ben Jone, S.R. Das	2006	6
17	Pseudorandom test-length analysis using differential solutions IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Dan Li, Wen-Ben Jone	1996	2
18	Realizing a high measure of confidence for defect level analysis of random testing [VLSI] IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Wen-Ben Jone, Cocieru Gabriela, Allan L. Gutjahr	1995	5
19	Timing optimization by gate resizing and critical path identification IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Chen-Liang Fang, Wen-Ben Jone	1995	7
20	Multiple fault detection in parity checkers IEEE Transactions on Computers ·Wen-Ben Jone, Friska Cony Safarita	1994	7

About Wen-Ben Jone

Wen-Ben Jone is a scholar working on Hardware and Architecture, Software, Electrical and Electronic Engineering, Computer Networks and Communications and Control and Systems Engineering, having authored 73 papers that have together received 825 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (48 papers), Integrated Circuits and Semiconductor Failure Analysis (34 papers), Low-power high-performance VLSI design (30 papers), Radiation Effects in Electronics (15 papers), VLSI and FPGA Design Techniques (11 papers), Parallel Computing and Optimization Techniques (11 papers), Semiconductor materials and devices (11 papers) and Embedded Systems Design Techniques (6 papers). The work is most often cited by research in Hardware and Architecture (540 citations), Computer Networks and Communications (389 citations), Electrical and Electronic Engineering (615 citations), Electronic, Optical and Magnetic Materials (108 citations) and Software (15 citations). Wen-Ben Jone has collaborated with scholars based in United States, Taiwan and Canada. Frequent co-authors include Qing-An Zeng, Ming Li, Ming Li, Ranga Vemuri, S.R. Das, Xingguo Xiong, Mansour H. Assaf, Emil M. Petriu, Yu‐Liang Wu and Yiming Hu. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Instrumentation and Measurement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ACM Transactions on Design Automation of Electronic Systems and IEEE Transactions on Reliability.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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