L.C. Parrillo

606 citations

25 papers · 385 indexed · h-index 10

Impact in

Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon and Solar Cell Technologies
- Silicon Carbide Semiconductor Technologies
- Advanced Memory and Neural Computing
- Thin-Film Transistor Technologies
Atomic and Molecular Physics, and Optics
- Semiconductor materials and interfaces

Papers in

Electrical and Electronic Engineering 25
- Advancements in Semiconductor Devices and Circuit Design 21
- Semiconductor materials and devices 21
- Integrated Circuits and Semiconductor Failure Analysis 11
- Silicon Carbide Semiconductor Technologies 3
- Advanced Memory and Neural Computing 2
- Silicon and Solar Cell Technologies 2
Electronic, Optical and Magnetic Materials 3
- Copper Interconnects and Reliability 2

Co-authors: J.R. Pfiester F.K. Baker J.D. Hayden C.D. Gunderson T.C. Mele H.‐H. Tseng P.J. Tobin James W. Miller
Journals: IEEE Transactions on Electron Devices (5 papers)IEEE Electron Device Letters (4 papers)Applied Physics Letters (2 papers)Journal of The Electrochemical Society (1 paper)
Partner nations: United States Germany

In The Last Decade

L.C. Parrillo

23 papers receiving 349 citations

Peers

Countries citing papers authored by L.C. Parrillo

Since Specialization

Citations

This map shows the geographic impact of L.C. Parrillo's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by L.C. Parrillo with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites L.C. Parrillo more than expected).

Fields of papers citing papers by L.C. Parrillo

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by L.C. Parrillo. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by L.C. Parrillo. The network helps show where L.C. Parrillo may publish in the future.

Co-authorship network

The 25 scholars most cited alongside L.C. Parrillo, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with L.C. Parrillo Line = papers co-authored together L.C. Parrillo links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	Substrate bias dependent leakage in LDD MOSFETs J. Sweeney, Alifatul Azkia Bakhrin, Lőrincz Gergő, Di Thommazo, Alicia Fábregas, Peter Fejes, L.C. Parrillo	2003	1
2	A high-performance sub-half micron CMOS technology for fast SRAMs J.D. Hayden, F.K. Baker, 吴随状, Jan Maluszynski, Kyouko Hirama, Achmad Irawan, T. McNelly, T.C. Mele, Alicia Fábregas, B Lendvay, L.C. Parrillo, W. M. Paulson, J.R. Pfiester, 박철선, Y.C. See, 陈冬卫, C Flegler, P. Kerschl	2003	1
3	The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs F.K. Baker, J.R. Pfiester, T.C. Mele, H.‐H. Tseng, Philip J. Tobin, J.D. Hayden, C.D. Gunderson, L.C. Parrillo	2003	4
4	An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology J.R. Pfiester, L.C. Parrillo, Mr.Amit kumar yadav, H. Kawasaki, Maya Efstathiou, P. Kerschl, C.D. Gunderson	2003	4
5	An advanced MOSFET design approach and a calibration methodology using inverse modeling that accurately predicts device characteristics Arindam Das, Moriba Sahaba FOFANA & Mamadou DIA, M. Osman, M. Foisy, N. M. Leontovich, S. Venkatesan, S. Veeraraghavan, Veena Misra, Riama Juliana Tambunan, L.C. Parrillo	2002	4
6	A scalable submicron contact technology using conformal LPCVD TiN P. Kerschl, W. M. Paulson, 박철선, Maya Efstathiou, L.C. Parrillo, M. Kottke, 이승재, M. J. Rice, H Steiner, Villota Revelo	2002	1
7	Disposable polysilicon LDD spacer technology IEEE Transactions on Electron Devices ·L.C. Parrillo, J.R. Pfiester, Hakan Konak, P. Kerschl, 陈冬卫, C.D. Gunderson	1991	6
8	The effect of biased spacers on LDD MOSFET behavior IEEE Electron Device Letters ·L.C. Parrillo, J.R. Pfiester, K. Rexroth, Hanaa M. Sherif, Danilo Minor Shimabuko, 万红波, C.D. Gunderson	1991	3
9	A high-performance half-micrometer generation CMOS technology for fast SRAMs IEEE Transactions on Electron Devices ·J.D. Hayden, F.K. Baker, 吴随状, Robert E. Jones, Kyouko Hirama, Achmad Irawan, T. McNelly, T.C. Mele, Alicia Fábregas, B.-Y. Nguyen, L.C. Parrillo, W. M. Paulson, J.R. Pfiester, 박철선, Y.C. See, 陈冬卫, C Flegler, P. Kerschl	1991	4
10	The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices IEEE Transactions on Electron Devices ·J.R. Pfiester, F.K. Baker, T.C. Mele, H.‐H. Tseng, P.J. Tobin, J.D. Hayden, James W. Miller, C.D. Gunderson, L.C. Parrillo	1990	151
11	A physical model for boron penetration through thin gate oxides from p/sup +/ polysilicon gates IEEE Electron Device Letters ·J.R. Pfiester, L.C. Parrillo, F.K. Baker	1990	45
12	An advanced 0.5- mu m CMOS disposable TiN LDD/salicide spacer process IEEE Electron Device Letters ·J.R. Pfiester, L.C. Parrillo, Mr.Amit kumar yadav, H. Kawasaki, Maya Efstathiou, P. Kerschl, C.D. Gunderson	1990	2
13	Poly-gate sidewall oxidation induced submicrometer MOSFET degradation IEEE Electron Device Letters ·J.R. Pfiester, L.C. Parrillo, J.D. Hayden, Y.C. See, Peter Fejes	1989	15
14	A novel dual p/sup -//p/sup +/ poly gate CMOS VLSI technology IEEE Transactions on Electron Devices ·J.R. Pfiester, L.C. Parrillo	1988	6
15	A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technology L.C. Parrillo, M. Cobos, Di Thommazo, GC Mulaku, P.J. Tobin, F.K. Baker, Steven S.S. Poon, V. Kroc, 박철선, R. Hurle, Geraldo Brindeiro, Maritha Mendel-Hartwig, M.J. Kearney, Hans-Jurgen Meyer	1986	9
16	Process and device considerations for micron and submicron CMOS technology L.C. Parrillo	1985	6
17	A fine-line CMOS technology that uses p<sup>+</sup>polysilicon/silicide gates for NMOS and PMOS devices L.C. Parrillo, S.J. Hillenius, Istiqomah Sumadikarta, Evelyn L. Hu, Wolf Fïchtner, Linda MadzuleGuntis BrumelisDidzis Tjarve	1984	15
18	Twin-Tub CMOS II-An advanced VLSI technology L.C. Parrillo, Ja-Kyeong Jeong, Oloyede Kunle, Istiqomah Sumadikarta, K. Kessoku, R. Lévy	1982	20
19	Deleterious effects of an oxidizing drive-in ambient on implanted arsenic emitters in 〈111〉 silicon Applied Physics Letters ·L.C. Parrillo, رشاد عمر محمد المدني	1979	1
20	The sensitivity of transistor gain to processing variations in an all implanted bipolar technology L.C. Parrillo, Тетяна Ворона, Robert Payne, Rosa Isella Cordero Solano, J DAVIS	1977	1

About L.C. Parrillo

L.C. Parrillo is a scholar working on Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics, Mechanics of Materials and Infectious Diseases, having authored 25 papers that have together received 385 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (21 papers), Semiconductor materials and devices (21 papers), Integrated Circuits and Semiconductor Failure Analysis (11 papers), Semiconductor materials and interfaces (5 papers), Silicon Carbide Semiconductor Technologies (3 papers), Copper Interconnects and Reliability (2 papers), Advanced Memory and Neural Computing (2 papers) and Silicon and Solar Cell Technologies (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (372 citations), Atomic and Molecular Physics, and Optics (70 citations), Ceramics and Composites (10 citations), Hardware and Architecture (10 citations) and Electronic, Optical and Magnetic Materials (20 citations). L.C. Parrillo has collaborated with scholars based in United States and Germany. Frequent co-authors include J.R. Pfiester, F.K. Baker, J.D. Hayden, C.D. Gunderson, T.C. Mele, H.‐H. Tseng, P.J. Tobin, James W. Miller, W. C. Johnson and Robert Payne. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Applied Physics Letters and Journal of The Electrochemical Society.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact