Mark Tehranipoor

2.8k total citations
104 papers, 1.7k citations indexed

About

Mark Tehranipoor is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Artificial Intelligence. According to data from OpenAlex, Mark Tehranipoor has authored 104 papers receiving a total of 1.7k indexed citations (citations by other indexed papers that have themselves been cited), including 97 papers in Hardware and Architecture, 71 papers in Electrical and Electronic Engineering and 32 papers in Artificial Intelligence. Recurrent topics in Mark Tehranipoor's work include Physical Unclonable Functions (PUFs) and Hardware Security (74 papers), Integrated Circuits and Semiconductor Failure Analysis (60 papers) and VLSI and Analog Circuit Testing (31 papers). Mark Tehranipoor is often cited by papers focused on Physical Unclonable Functions (PUFs) and Hardware Security (74 papers), Integrated Circuits and Semiconductor Failure Analysis (60 papers) and VLSI and Analog Circuit Testing (31 papers). Mark Tehranipoor collaborates with scholars based in United States, Japan and France. Mark Tehranipoor's co-authors include Domenic Forte, Farimah Farahmandi, Swarup Bhunia, Mehrdad Nourani, Fahim Rahman, Xuehui Zhang, Nisar Ahmed, Krishnendu Chakrabarty, Prabhat Mishra and Jim Plusquellic and has published in prestigious journals such as IEEE Access, IEEE Transactions on Information Forensics and Security and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Mark Tehranipoor

99 papers receiving 1.6k citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Mark Tehranipoor United States 24 1.4k 1.2k 476 251 223 104 1.7k
Nozomu Togawa Japan 21 1.4k 1.0× 1.3k 1.1× 746 1.6× 252 1.0× 184 0.8× 283 2.0k
Anirban Sengupta India 19 888 0.6× 585 0.5× 293 0.6× 199 0.8× 280 1.3× 159 1.2k
Selçuk Baktır Türkiye 10 569 0.4× 560 0.5× 297 0.6× 211 0.8× 111 0.5× 30 874
Jim Plusquellic United States 29 2.5k 1.8× 2.2k 1.9× 726 1.5× 849 3.4× 346 1.6× 126 3.0k
Christian Pilato Italy 18 1.1k 0.8× 558 0.5× 220 0.5× 136 0.5× 86 0.4× 85 1.3k
Avesta Sasan United States 22 818 0.6× 665 0.6× 614 1.3× 174 0.7× 452 2.0× 100 1.4k
Farimah Farahmandi United States 18 816 0.6× 511 0.4× 470 1.0× 166 0.7× 183 0.8× 135 1.1k
Pramod Subramanyan United States 16 970 0.7× 860 0.7× 422 0.9× 275 1.1× 197 0.9× 31 1.2k
Fahim Rahman United States 14 449 0.3× 345 0.3× 205 0.4× 112 0.4× 101 0.5× 58 668
Jiliang Zhang China 14 566 0.4× 532 0.5× 286 0.6× 242 1.0× 201 0.9× 40 944

Countries citing papers authored by Mark Tehranipoor

Since Specialization
Citations

This map shows the geographic impact of Mark Tehranipoor's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Mark Tehranipoor with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Mark Tehranipoor more than expected).

Fields of papers citing papers by Mark Tehranipoor

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Mark Tehranipoor. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Mark Tehranipoor. The network helps show where Mark Tehranipoor may publish in the future.

Co-authorship network of co-authors of Mark Tehranipoor

This figure shows the co-authorship network connecting the top 25 collaborators of Mark Tehranipoor. A scholar is included among the top collaborators of Mark Tehranipoor based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Mark Tehranipoor. Mark Tehranipoor is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Farahmandi, Farimah, et al.. (2025). NoXLock: SiP Activation and Licensing through Obfuscated on-Chip Network and Fuzzy Traffic. 788–793. 1 indexed citations
3.
Azar, Kimia Zamiri, et al.. (2024). Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration. IEEE Transactions on Information Forensics and Security. 19. 2771–2785.
4.
5.
Zhou, Jingbo, et al.. (2024). SYSFID—System-Aware Fault-Injection Attack Detection for System-In-Package Architectures. Proceedings - International Symposium for Testing and Failure Analysis. 84918. 332–341. 1 indexed citations
6.
7.
Azar, Kimia Zamiri, et al.. (2023). Understanding Logic Locking. 5 indexed citations
8.
Tehranipoor, Mark, et al.. (2022). ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features. 155–164. 1 indexed citations
9.
Rahman, Fahim, et al.. (2021). ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(10). 3202–3215. 13 indexed citations
10.
Kastner, Ryan, et al.. (2021). Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions. 1–10. 6 indexed citations
11.
Rahman, Fahim, et al.. (2021). SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(3). 452–465. 27 indexed citations
12.
Rahman, Fahim, et al.. (2019). EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection Using Machine Learning Classification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28(2). 363–375. 17 indexed citations
13.
Ganji, Fatemeh, et al.. (2019). The Power of IC Reverse Engineering for Hardware Trust and Assurance. 21(2). 30–36. 1 indexed citations
14.
Guin, Ujjwal, Navid Asadizanjani, & Mark Tehranipoor. (2019). Standards for Hardware Security. GetMobile Mobile Computing and Communications. 23(1). 5–9. 7 indexed citations
15.
Rahman, Fahim, et al.. (2019). SoC Security Verification using Property Checking. 1–10. 31 indexed citations
16.
Nahiyan, Adib, et al.. (2017). Security vulnerability analysis of design-for-test exploits for asset protection in SoCs. 617–622. 29 indexed citations
17.
Yang, Kun, Domenic Forte, & Mark Tehranipoor. (2017). CDTA. ACM Transactions on Design Automation of Electronic Systems. 22(3). 1–31. 37 indexed citations
18.
Karam, Robert, et al.. (2016). Robust bitstream protection in FPGA-based systems through low-overhead obfuscation. 1–8. 31 indexed citations
19.
Forte, Domenic, et al.. (2014). Aging analysis for recycled FPGA detection. 171–176. 62 indexed citations
20.
Dilillo, Luigi, Alberto Bosio, Patrick Girard, et al.. (2010). Is test power reduction through X-filling good enough?. 1–1. 5 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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