P. Coteus
- Hardware and Architecture top 1%
- Parallel Computing and Optimization Techniques 8
- Embedded Systems Design Techniques 4
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- Interconnection Networks and Systems 7
- Advanced Data Storage Technologies 5
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- 3D IC and TSV technologies 15
- Electromagnetic Compatibility and Noise Suppression 13
- Low-power high-performance VLSI design 8
- Electronic Packaging and Soldering Technologies 5
- Information Systems top 5%
- Co-authors
- A. DeutschAlan GaraG.V. KopcsayC.W. SurovicMatthias A. BlumrichTodd TakkenMark GiampapaPavlos Vranas
- Cited by
- Hardware and ArchitectureComputer Networks and CommunicationsElectrical and Electronic Engineering
- Journals
- IBM Journal of Research and Development (6 papers)Proceedings of the IEEE (2 papers)IEEE Transactions on Advanced Packaging (2 papers)
- Partner nations
- United StatesIndiaSouth Korea
In The Last Decade
P. Coteus
36 papers receiving 1.6k citations
Peers
Comparison fields: 5 of 66
- Hardware and Architecture 611
- Computer Networks and Communications 647
- Electrical and Electronic Engineering 1.0k
- Information Systems 110
- Computational Theory and Mathematics 61
Countries citing papers authored by P. Coteus
This map shows the geographic impact of P. Coteus's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P. Coteus with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P. Coteus more than expected).
Fields of papers citing papers by P. Coteus
This network shows the impact of papers produced by P. Coteus. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P. Coteus. The network helps show where P. Coteus may publish in the future.
Co-authorship network
The 25 scholars most cited alongside P. Coteus, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2019 | 29 | |
| 2 | 2018 | 22 | |
| 3 | 2017 | 5 | |
| 4 | 2013 | 6 | |
| 5 | 2010 | 146 | |
| 6 | 2008 | 26 | |
| 7 | 2005 | 238 | |
| 8 | 2005 | 19 | |
| 9 | 2005 | 32 | |
| 10 | 2005 | 248 | |
| 11 | 2003 | 4 | |
| 12 | IBM Research Report Design and Analysis of the BlueGene/L Torus Interconnection Network | 2003 | 24 |
| 13 | 2002 | 1 | |
| 14 | 2002 | 14 | |
| 15 | 2002 | 0 | |
| 16 | 2002 | 6 | |
| 17 | 2001 | 149 | |
| 18 | 1999 | 28 | |
| 19 | 1997 | 10 | |
| 20 | 1996 | 12 |
About P. Coteus
P. Coteus is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Automotive Engineering and Nuclear and High Energy Physics, having authored 40 papers that have together received 1.7k indexed citations. Recurring topics across this work include 3D IC and TSV technologies (15 papers), Electromagnetic Compatibility and Noise Suppression (13 papers), Low-power high-performance VLSI design (8 papers), Parallel Computing and Optimization Techniques (8 papers), Interconnection Networks and Systems (7 papers), Advanced Data Storage Technologies (5 papers), Electronic Packaging and Soldering Technologies (5 papers) and Embedded Systems Design Techniques (4 papers). The work is most often cited by research in Hardware and Architecture (611 citations), Computer Networks and Communications (647 citations), Electrical and Electronic Engineering (1.0k citations), Information Systems (110 citations) and Computational Theory and Mathematics (61 citations). P. Coteus has collaborated with scholars based in United States, India and South Korea. Frequent co-authors include A. Deutsch, Alan Gara, G.V. Kopcsay, C.W. Surovic, Matthias A. Blumrich, Todd Takken, Mark Giampapa, Pavlos Vranas, H.H. Smith and B. Krauter. Their work appears in journals such as IBM Journal of Research and Development, Proceedings of the IEEE, IEEE Transactions on Advanced Packaging, IEEE Journal of Solid-State Circuits and IEEE Micro.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.