Robert K. Montoye

2.8k total citations · 1 hit paper
41 papers, 2.1k citations indexed

About

Robert K. Montoye is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Robert K. Montoye has authored 41 papers receiving a total of 2.1k indexed citations (citations by other indexed papers that have themselves been cited), including 31 papers in Electrical and Electronic Engineering, 15 papers in Hardware and Architecture and 12 papers in Computer Networks and Communications. Recurrent topics in Robert K. Montoye's work include Low-power high-performance VLSI design (22 papers), Parallel Computing and Optimization Techniques (11 papers) and Advancements in Semiconductor Devices and Circuit Design (11 papers). Robert K. Montoye is often cited by papers focused on Low-power high-performance VLSI design (22 papers), Parallel Computing and Optimization Techniques (11 papers) and Advancements in Semiconductor Devices and Circuit Design (11 papers). Robert K. Montoye collaborates with scholars based in United States, Japan and Slovakia. Robert K. Montoye's co-authors include E. Hökenek, R.H. Dennard, Wilfried Haensch, Leland Chang, Steve Runyon, L. Chang, Damir A. Jamsek, Yutaka Nakamura, Richard J. Eickemeyer and J.W. Sleight and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IBM Journal of Research and Development.

In The Last Decade

Robert K. Montoye

39 papers receiving 2.0k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Stable SRAM cell design for the 32 nm node and beyond

2005 449 citations L. Chang, R.H. Dennard et al. profile →

Peers

Countries citing papers authored by Robert K. Montoye

Since Specialization

Citations

This map shows the geographic impact of Robert K. Montoye's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Robert K. Montoye with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Robert K. Montoye more than expected).

Fields of papers citing papers by Robert K. Montoye

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Robert K. Montoye. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Robert K. Montoye. The network helps show where Robert K. Montoye may publish in the future.

Co-authorship network of co-authors of Robert K. Montoye

This figure shows the co-authorship network connecting the top 25 collaborators of Robert K. Montoye. A scholar is included among the top collaborators of Robert K. Montoye based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Robert K. Montoye. Robert K. Montoye is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI 2013 ·Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, L. Chang, J. Tierno, Daniel J. Friedman	15
2	A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons 2011 ·Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman	264
3	A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation 2011 ·(unknown), Robert K. Montoye, (unknown), (unknown), (unknown), Bruce Fleischer, Thomas Fox, (unknown), (unknown), Yutaka Nakamura, (unknown), (unknown), (unknown), Leland Chang	22
4	Demonstration of CAM and TCAM Using Phase Change Devices 2011 ·Bipin Rajendran, R. Cheek, Luis Lastras, Michele Franceschini, M. Breitwisch, A. G. Schrott, Jing Li, Robert K. Montoye, Leland Chang, Chung Lam	25
5	A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm<sup>2</sup> 2010 ·Leland Chang, Robert K. Montoye, (unknown), Alan J. Weger, Kevin Stawiasz, R.H. Dennard	116
6	Practical Strategies for Power-Efficient Computing Technologies 2010 ·Proceedings of the IEEE ·L. Chang, D.J. Frank, Robert K. Montoye, Steven J. Koester, Baoxian Ji, P. Coteus, R.H. Dennard, Wilfried Haensch	146
7	A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit 2009 ·Journal of Signal Processing Systems ·Xiao Yan Zhang, (unknown), Robert K. Montoye, L. Sigal, E. Schwarz, Michael Kelly	4
8	An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches 2008 ·IEEE Journal of Solid-State Circuits ·Leland Chang, Robert K. Montoye, Yutaka Nakamura, (unknown), Richard J. Eickemeyer, R.H. Dennard, Wilfried Haensch, Damir A. Jamsek	307
9	A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS 2007 ·Leland Chang, Yutaka Nakamura, Robert K. Montoye, Jun Sawada, Andrew Martin, (unknown), Fadi H. Gebara, Kanak Agarwal, Dhruva Acharyya, Wilfried Haensch, Kohji Hosokawa, Damir A. Jamsek	104
10	Testing and debugging delay faults in dynamic circuits 2006 ·(unknown), Sani Nassif, Robert K. Montoye, Jacob A. Abraham	4
11	Controlled-Load Limited Switch Dynamic Logic Circuit 2005 ·(unknown), Hùng Ngô, Kevin Nowka, Robert K. Montoye, Richard B. Brown	5
12	An 8Ghz floating-point multiply 2005 ·Wendy Belluomini, Damir A. Jamsek, Andrew Martin, C. McDowell, Robert K. Montoye, Tuyet Nguyen, Hùng Ngô, Jun Sawada, Ivan Vo, (unknown)	15
13	A 64b 4-issue out-of-order execution RISC processor 2002 ·(unknown), (unknown), Hisao Ando, (unknown), (unknown), Chien Chen, (unknown), (unknown), (unknown), Takeshi Kitahara, Hungwen Li, (unknown), Robert K. Montoye, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Ted E. Williams	6
14	A decompression core for PowerPC 1998 ·IBM Journal of Research and Development ·(unknown), Robert K. Montoye, (unknown), John D. Palmer, Daniel J. Auerbach	72
15	Design of the IBM RISC System/6000 floating-point execution unit 1995 ·IEEE Computer Society Press eBooks ·Robert K. Montoye, E. Hökenek, Steve Runyon	34
16	Second-generation RISC floating point with multiply-add fused 1990 ·IEEE Journal of Solid-State Circuits ·E. Hökenek, Robert K. Montoye, Peter W. Cook	90
17	An 18 ns 56-bit multiply-adder circuit 1990 ·Robert K. Montoye, Peter W. Cook, E. Hökenek, (unknown)	14
18	Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit 1990 ·IBM Journal of Research and Development ·E. Hökenek, Robert K. Montoye	59
19	Automatically generated area, power and delay optimized ALUs 1983 ·Robert K. Montoye, Peter W. Cook	3
20	AREA-Time Efficient Addition in Charge Based Technology 1981 ·Design Automation Conference ·Robert K. Montoye	8

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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