Olivier Billoint

982 total citations
42 papers, 376 citations indexed

About

Olivier Billoint is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Hardware and Architecture. According to data from OpenAlex, Olivier Billoint has authored 42 papers receiving a total of 376 indexed citations (citations by other indexed papers that have themselves been cited), including 40 papers in Electrical and Electronic Engineering, 8 papers in Computer Networks and Communications and 6 papers in Hardware and Architecture. Recurrent topics in Olivier Billoint's work include 3D IC and TSV technologies (21 papers), Semiconductor materials and devices (19 papers) and Advanced Memory and Neural Computing (11 papers). Olivier Billoint is often cited by papers focused on 3D IC and TSV technologies (21 papers), Semiconductor materials and devices (19 papers) and Advanced Memory and Neural Computing (11 papers). Olivier Billoint collaborates with scholars based in France, Switzerland and Norway. Olivier Billoint's co-authors include Sébastien Thuries, P. Batude, Édith Beigné, Blaise Yvert, Guillaume Charvet, C. Fenouillet-Béranger, Fabien Deprat, Jean-Pierre Rostaing, M. Vinet and F. Clermidy and has published in prestigious journals such as Biosensors and Bioelectronics, IEEE Journal of Solid-State Circuits and IEEE Electron Device Letters.

In The Last Decade

Olivier Billoint

38 papers receiving 370 citations

Peers

Countries citing papers authored by Olivier Billoint

Since Specialization

Citations

This map shows the geographic impact of Olivier Billoint's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Olivier Billoint with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Olivier Billoint more than expected).

Fields of papers citing papers by Olivier Billoint

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Olivier Billoint. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Olivier Billoint. The network helps show where Olivier Billoint may publish in the future.

Co-authorship network of co-authors of Olivier Billoint

This figure shows the co-authorship network connecting the top 25 collaborators of Olivier Billoint. A scholar is included among the top collaborators of Olivier Billoint based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Olivier Billoint. Olivier Billoint is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Dual-Mode 16kb Memory: Transforming a Ferroelectric Capacitor Bitcell into Resistive Filamentary Memory 2025 ·SPIRE - Sciences Po Institutional REpository ·(unknown), Olivier Billoint, L. Grenouillet, Sébastien Martin, J.M. Portal, (unknown)	0
2	Hybrid FeRAM/RRAM Synaptic Circuit Enabling On-Chip Inference and Learning at the Edge 2023 ·SPIRE - Sciences Po Institutional REpository ·(unknown), (unknown), Tifenn Hirtzlin, Sébastien Martin, (unknown), (unknown), C. Carabasse, Olivier Billoint, (unknown), J. Coignus, Adrien F. Vincent, Damien Querlioz, L. Grenouillet, Sylvain Saïghi, Elisa Vianello	5
3	RRAM Device Performances Under Capacitive-Enhanced Current Programming Scheme 2023 ·IEEE Electron Device Letters ·(unknown), (unknown), Olivier Billoint, (unknown), (unknown), G. Molas, Gaël Pillonnet	2
4	M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC 2020 ·HAL (Le Centre pour la Communication Scientifique Directe) ·Sébastien Thuries, Olivier Billoint, (unknown), R. Lemaire, Pascal Vivet, P. Batude, Didier Lattard	8
5	Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology 2019 ·IEEE Transactions on Circuits & Systems II Express Briefs ·Dimitri Galayko, (unknown), (unknown), Mohammad Mahdi Javidan, (unknown), (unknown), Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard	5
6	A partitioning-free methodology for optimized gate-level monolithic 3D designs 2017 ·Olivier Billoint, (unknown), Sébastien Thuries, (unknown), (unknown)	3
7	From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose 2016 ·G. Cibrario, (unknown), J. Lacord, (unknown), O. Rozeau, (unknown), Olivier Billoint, Sébastien Thuries, Alexandre Valentian	1
8	High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology 2016 ·(unknown), (unknown), J.-P. Noël, (unknown), Bastien Giraud, Édith Beigné, David Turgis, Sébastien Thuries, (unknown), Olivier Billoint	7
9	Recent advances in 3D VLSI integration 2016 ·C. Fenouillet-Béranger, P. Batude, Laurent Brunet, V. Mazzocchi, (unknown), Fabien Deprat, (unknown), M.-P. Samson, B. Prévitali, (unknown), N. Rambal, F. Andrieu, Olivier Billoint, (unknown), Sébastien Thuries, G. Cibrario, M. Vinet	1
10	Impact of intermediate BEOL technology on standard cell performances of 3D VLSI 2016 ·(unknown), (unknown), Sébastien Thuries, F. Clermidy, P. Batude, C. Fenouillet-Béranger, Laurent Brunet, F. Andrieu, Fabien Deprat, J. Lacord, O. Rozeau, G. Cibrario, Olivier Billoint	7
11	UTBB FDSOI technology flexibility for ultra low power internet-of-things applications 2015 ·Édith Beigné, (unknown), Alexandre Valentian, Olivier Billoint, E. Amat, Dominique Morche	22
12	From 2D to Monolithic 3D 2015 ·Olivier Billoint, (unknown), (unknown), M. Vinet, P. Batude, C. Fenouillet-Béranger, O. Rozeau, G. Cibrario, Fabien Deprat, Ogun Turkyilmaz, Sébastien Thuries, Fabien Clermidy	6
13	FDSOI Suitability for Asynchronous Circuits at Sub-V_T 2015 ·ECS Transactions ·E. Amat, (unknown), Olivier Billoint, (unknown), Édith Beigné	3
14	A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool 2015 ·Olivier Billoint, (unknown), (unknown), M. Vinet, P. Batude, C. Fenouillet-Béranger, O. Rozeau, G. Cibrario, Fabien Deprat, (unknown), (unknown), O. Faynot, Ogun Turkyilmaz, (unknown), Sébastien Thuries, F. Clermidy	22
15	3D technologies for reconfigurable architectures 2014 ·F. Clermidy, (unknown), Olivier Billoint, P.-E. Gaillardon	0
16	3DCoB: A new design approach for Monolithic 3D Integrated circuits 2014 ·(unknown), Sébastien Thuries, Olivier Billoint, Fabien Clermidy	5
17	A modular 256-channel Micro Electrode Array platform for in vitro and in vivo neural stimulation and recording: BioMEA™ 2010 ·PubMed ·Guillaume Charvet, Olivier Billoint, (unknown), Marc Olivier Heuschkel, (unknown), Thomas Kauffmann, (unknown), Blaise Yvert, R. Guillemaud	7
18	BioMEA™: A versatile high-density 3D microelectrode array system using integrated electronics 2010 ·Biosensors and Bioelectronics ·Guillaume Charvet, Lionel Rousseau, Olivier Billoint, (unknown), Jean-Pierre Rostaing, Sébastien Joucla, (unknown), (unknown), (unknown), (unknown), (unknown), Bruno Mercier, (unknown), (unknown), Hervé Fanet, Pierre Meyrand, R. Guillemaud, Blaise Yvert	61
19	BioMEA¿ : A 256-channel MEA system with integrated electronics 2007 ·Conference proceedings ·Guillaume Charvet, Olivier Billoint, Lionel Rousseau, Blaise Yvert	5
20	A 64-Channel ASIC for In-Vitro Simultaneous Recording and Stimulation of Neurons using Microelectrode Arrays 2007 ·Conference proceedings ·Olivier Billoint, Jean-Pierre Rostaing, Guillaume Charvet, Blaise Yvert	11

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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