B. Duriez

745 total citations
36 papers, 433 citations indexed

About

B. Duriez is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Condensed Matter Physics. According to data from OpenAlex, B. Duriez has authored 36 papers receiving a total of 433 indexed citations (citations by other indexed papers that have themselves been cited), including 34 papers in Electrical and Electronic Engineering, 7 papers in Biomedical Engineering and 4 papers in Condensed Matter Physics. Recurrent topics in B. Duriez's work include Advancements in Semiconductor Devices and Circuit Design (28 papers), Semiconductor materials and devices (27 papers) and Integrated Circuits and Semiconductor Failure Analysis (7 papers). B. Duriez is often cited by papers focused on Advancements in Semiconductor Devices and Circuit Design (28 papers), Semiconductor materials and devices (27 papers) and Integrated Circuits and Semiconductor Failure Analysis (7 papers). B. Duriez collaborates with scholars based in France, Taiwan and United States. B. Duriez's co-authors include G. Vellianitis, M.J.H. van Dal, G. Doornbos, C.H. Diaz, M. Passlack, M. Holland, Aryan Afzalian, C.H. Hsieh, Krishna K. Bhuwalka and Dominique Fleury and has published in prestigious journals such as SHILAP Revista de lepidopterología, Scientific Reports and IEEE Transactions on Electron Devices.

In The Last Decade

B. Duriez

28 papers receiving 418 citations

Peers

B. Duriez

EEE

AMPO

Rafael Rios United States

B. Cretu France

P. Ribot France

S. Locorotondo Belgium

K. Schruefer United States

F. Nouri United States

Craig Riddet United Kingdom

Shiying Xiong United States

R. Palla France

Shyam Raghunathan United States

Rafael Rios United States

B. Duriez

426 ×1.0

EEE

108 ×0.8

35 ×0.5

AMPO

37 ×1.4

4 ×0.7

Citations per year, relative to B. Duriez B. Duriez (= 1×) peers Rafael Rios

Countries citing papers authored by B. Duriez

Since Specialization

Citations

This map shows the geographic impact of B. Duriez's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by B. Duriez with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites B. Duriez more than expected).

Fields of papers citing papers by B. Duriez

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by B. Duriez. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by B. Duriez. The network helps show where B. Duriez may publish in the future.

Co-authorship network of co-authors of B. Duriez

This figure shows the co-authorship network connecting the top 25 collaborators of B. Duriez. A scholar is included among the top collaborators of B. Duriez based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with B. Duriez. B. Duriez is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Rodriguez, Philippe, et al.. (2025). Toward full relaxation of sSOI substrates for PFET device fabrication. Solid-State Electronics. 229. 109196–109196.

Gobil, Y., et al.. (2025). Forward gate current modeling of AlGaN/AlN/GaN HEMTs based on Poisson–Schrödinger and direct tunneling equations. SHILAP Revista de lepidopterología. 1(3).

Lucci, Luca, Y. Gobil, Antonio Clemente, et al.. (2024). CMOS Compatible 200 mm GaN-on-Si HEMTs for RF Switch Applications with 36 dBm CW Power Handling and 200 FS RonCoff. 1–4.

Hartmann, Jean‐Michel, F. Aussenac, David Cooper, et al.. (2024). Advanced SiGe:B Raised Sources and Drains for p-type FD-SOI MOSFETs. ECS Transactions. 114(2). 185–205. 1 indexed citations

Blonkowski, S., X. Federspiel, Dibyendu Roy, et al.. (2024). Fine Characterization and Modeling of the Frequency Dependence of TDDB in RF Domain (F>10GHz). 1–4.

Lucci, Luca, M. Grégoire, P. Chevalier, et al.. (2024). Enhanced RF Switch Performance in RFSOI Technology: Achieving 74 fs R_ON·C_OFF and 3.3 V RFV_MAX on Thinned SOI. SPIRE - Sciences Po Institutional REpository. 448–451.

Duriez, B., S. Reboh, Jean‐Michel Hartmann, et al.. (2023). Computational model for predicting structural stability and stress transfer of a new SiGe stressor technique for NMOS devices. Solid-State Electronics. 210. 108787–108787.

Garros, X., S. Crémer, V. Knopik, et al.. (2023). A cost effective RF-SOI Drain Extended MOS transistor featuring P _SAT =19dBm @28GHz & V _DD =3V for 5G Power Amplifier application. SPIRE - Sciences Po Institutional REpository. 1–4. 1 indexed citations

Dal, M.J.H. van, G. Vellianitis, G. Doornbos, et al.. (2018). Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs. 21.1.1–21.1.4. 36 indexed citations

10.

Holland, M., Mark van Dal, B. Duriez, et al.. (2017). Atomically flat and uniform relaxed III–V epitaxial films on silicon substrate for heterogeneous and hybrid integration. Scientific Reports. 7(1). 14632–14632. 5 indexed citations

11.

Doornbos, G., M. Holland, G. Vellianitis, et al.. (2016). High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates. IEEE Journal of the Electron Devices Society. 4(5). 253–259. 12 indexed citations

12.

Vasen, T., P. Ramvall, Aryan Afzalian, et al.. (2016). InAs nanowire GAA n-MOSFETs with 12–15 nm diameter. Lund University Publications (Lund University). 1–2. 15 indexed citations

13.

Dal, M.J.H. van, G. Vellianitis, B. Duriez, et al.. (2014). Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping. IEEE Transactions on Electron Devices. 61(2). 430–436. 48 indexed citations

14.

Vellianitis, G., M.J.H. van Dal, B. Duriez, et al.. (2013). High crystalline quality Ge grown by MOCVD inside narrow shallow trench isolation defined on Si(001) substrates. Journal of Crystal Growth. 383. 9–11. 8 indexed citations

15.

Chang, S. W., Xu Li, M.J.H. van Dal, et al.. (2012). An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III–V NMOS. IEEE Electron Device Letters. 33(4). 501–503. 30 indexed citations

16.

Curatola, G., A. Nackaerts, Nadine Collaert, et al.. (2008). First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling. 1–4. 21 indexed citations

17.

Vellianitis, G., Ray Duffy, G. Doornbos, et al.. (2008). Material Aspects and Challenges for SOI FinFET Integration. ECS Transactions. 13(1). 223–234. 5 indexed citations

18.

Bœuf, F., Mathieu Sellier, B. Duriez, et al.. (2006). Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation. 1 indexed citations

19.

Chanemougame, D., S. Monfray, F. Bœuf, et al.. (2005). Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS. 180–181. 7 indexed citations

20.

Duriez, B., A. Grouillet, F. Arnaud, et al.. (2004). Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping. 178–179. 10 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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