Igor Loi

2.5k total citations
59 papers, 1.6k citations indexed

About

Igor Loi is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Hardware and Architecture. According to data from OpenAlex, Igor Loi has authored 59 papers receiving a total of 1.6k indexed citations (citations by other indexed papers that have themselves been cited), including 47 papers in Electrical and Electronic Engineering, 42 papers in Computer Networks and Communications and 36 papers in Hardware and Architecture. Recurrent topics in Igor Loi's work include Interconnection Networks and Systems (40 papers), Parallel Computing and Optimization Techniques (33 papers) and Advanced Memory and Neural Computing (22 papers). Igor Loi is often cited by papers focused on Interconnection Networks and Systems (40 papers), Parallel Computing and Optimization Techniques (33 papers) and Advanced Memory and Neural Computing (22 papers). Igor Loi collaborates with scholars based in Italy, Switzerland and France. Igor Loi's co-authors include Luca Benini, Davide Rossi, Antonio Pullini, Francesco Conti, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Thomas H. Lee, Giuseppe Tagliavini and Mohammad Reza Kakoee and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Solid-State Electronics.

In The Last Decade

Igor Loi

59 papers receiving 1.5k citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Igor Loi Italy 22 1.1k 710 645 204 129 59 1.6k
Antonio Pullini Italy 23 1.0k 0.9× 655 0.9× 711 1.1× 227 1.1× 174 1.3× 56 1.6k
Édith Beigné France 19 989 0.9× 417 0.6× 483 0.7× 111 0.5× 120 0.9× 108 1.3k
David Fick United States 21 1.4k 1.3× 678 1.0× 651 1.0× 95 0.5× 276 2.1× 31 1.8k
Kambiz Samadi United States 21 1.3k 1.2× 805 1.1× 791 1.2× 166 0.8× 85 0.7× 49 1.8k
Pascal Vivet France 22 1.3k 1.2× 810 1.1× 836 1.3× 40 0.2× 77 0.6× 113 1.7k
Matthew Fojtik United States 18 1.0k 0.9× 253 0.4× 485 0.8× 223 1.1× 148 1.1× 32 1.3k
Arnab Raha United States 22 1.1k 1.0× 442 0.6× 502 0.8× 123 0.6× 144 1.1× 89 1.5k
Xuan Zhang United States 19 791 0.7× 206 0.3× 258 0.4× 165 0.8× 196 1.5× 90 1.4k
Noriyuki Miura Japan 22 1.5k 1.3× 313 0.4× 471 0.7× 98 0.5× 209 1.6× 172 1.8k

Countries citing papers authored by Igor Loi

Since Specialization
Citations

This map shows the geographic impact of Igor Loi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Igor Loi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Igor Loi more than expected).

Fields of papers citing papers by Igor Loi

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Igor Loi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Igor Loi. The network helps show where Igor Loi may publish in the future.

Co-authorship network of co-authors of Igor Loi

This figure shows the co-authorship network connecting the top 25 collaborators of Igor Loi. A scholar is included among the top collaborators of Igor Loi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Igor Loi. Igor Loi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Loi, Igor, et al.. (2023). Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 31(4). 456–469. 2 indexed citations
2.
Rossi, Davide, Francesco Conti, Manuel Eggimann, et al.. (2021). Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE Journal of Solid-State Circuits. 57(1). 127–139. 65 indexed citations
3.
Loi, Igor, et al.. (2020). Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster. Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna). 1734–1739. 4 indexed citations
4.
Flamand, Éric, Davide Rossi, Francesco Conti, et al.. (2018). GAP-8: A RISC-V SoC for AI at the Edge of the IoT. Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna). 1–4. 143 indexed citations
5.
Rossi, Davide, et al.. (2016). Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25(1). 210–223. 22 indexed citations
6.
Rossi, Davide, et al.. (2016). A Case for Near Memory Computation Inside the Smart Memory Cube. Publication Server of Kaiserslautern University of Technology (Kaiserslautern University of Technology). 3 indexed citations
7.
Rossi, Davide, Francesco Conti, Andrea Marongiu, et al.. (2015). PULP: A parallel ultra low power platform for next generation IoT applications. Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna). 1–39. 86 indexed citations
8.
Rossi, Davide, et al.. (2015). High performance AXI-4.0 based interconnect for extensible smart memory cubes. Design, Automation, and Test in Europe. 1317–1322. 19 indexed citations
9.
Rossi, Davide, et al.. (2015). High Performance AXI-4.0 Based Interconnect for Extensible Smart Memory Cubes. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. 1317–1322. 16 indexed citations
10.
Rossi, Davide, et al.. (2014). A Modular Shared L2 Memory Design for 3-D Integration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(8). 1485–1498. 4 indexed citations
11.
Loi, Igor, et al.. (2013). A high-performance multiported L2 memory IP for scalable three-dimensional integration. Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna). 37. 1–8. 1 indexed citations
12.
Kakoee, Mohammad Reza, Igor Loi, & Luca Benini. (2012). A resilient architecture for low latency communication in shared-L1 processor clusters. Design, Automation, and Test in Europe. 887–892. 7 indexed citations
13.
Weis, Christian, Igor Loi, Luca Benini, & Norbert Wehn. (2012). An energy efficient DRAM subsystem for 3D integrated SoCs. Design, Automation, and Test in Europe. 1138–1141. 12 indexed citations
14.
15.
Kakoee, Mohammad Reza, Igor Loi, & Luca Benini. (2012). Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters. IEEE Transactions on Circuits & Systems II Express Briefs. 59(12). 927–931. 13 indexed citations
16.
Loi, Igor, et al.. (2010). 3D NoCs — Unifying inter & intra chip communication. 1. 3337–3340. 5 indexed citations
17.
Loi, Igor & Luca Benini. (2010). An efficient distributed memory interface for many-core platform with 3D stacked DRAM. Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna). 99–104. 21 indexed citations
18.
Loi, Igor, Federico Angiolini, & Luca Benini. (2009). Synthesis of low-overhead configurable source routing tables for network interfaces. Design, Automation, and Test in Europe. 262–267. 6 indexed citations
19.
Loi, Igor, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, & Luca Benini. (2008). A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. International Conference on Computer Aided Design. 598–602. 120 indexed citations
20.
Loi, Igor, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, & Luca Benini. (2008). A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. 598–602. 125 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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