S. Ohbayashi

812 total citations
27 papers, 582 citations indexed

About

S. Ohbayashi is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Surgery. According to data from OpenAlex, S. Ohbayashi has authored 27 papers receiving a total of 582 indexed citations (citations by other indexed papers that have themselves been cited), including 26 papers in Electrical and Electronic Engineering, 7 papers in Hardware and Architecture and 1 paper in Surgery. Recurrent topics in S. Ohbayashi's work include Low-power high-performance VLSI design (20 papers), Semiconductor materials and devices (19 papers) and Advancements in Semiconductor Devices and Circuit Design (17 papers). S. Ohbayashi is often cited by papers focused on Low-power high-performance VLSI design (20 papers), Semiconductor materials and devices (19 papers) and Advancements in Semiconductor Devices and Circuit Design (17 papers). S. Ohbayashi collaborates with scholars based in Japan, United States and South Korea. S. Ohbayashi's co-authors include Yasumasa Tsukamoto, Hirofumi Shinohara, Hiroshi Makino, Koji Nii, Makoto Yabuuchi, Susumu Imaoka, Koichiro Ishibashi, H. Akamatsu, Hiroshi Kawashima and Yasuo Yamaguchi and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, ACM Transactions on Design Automation of Electronic Systems and IEICE technical report. Speech.

In The Last Decade

S. Ohbayashi

26 papers receiving 559 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
S. Ohbayashi Japan 12 564 141 28 24 8 27 582
Yong-Gee Ng United States 13 535 0.9× 113 0.8× 18 0.6× 21 0.9× 14 1.8× 16 553
Tomoaki Yabe Japan 11 320 0.6× 79 0.6× 18 0.6× 44 1.8× 5 0.6× 23 330
Y. Yamagami Japan 9 350 0.6× 93 0.7× 13 0.5× 14 0.6× 3 0.4× 17 353
A.J. Bhavnagarwala United States 11 1.1k 1.9× 276 2.0× 28 1.0× 50 2.1× 13 1.6× 24 1.1k
Y. Takeyama Japan 12 389 0.7× 86 0.6× 22 0.8× 45 1.9× 6 0.8× 27 399
Osamu Hirabayashi Japan 10 333 0.6× 81 0.6× 19 0.7× 43 1.8× 3 0.4× 25 340
Uddalak Bhattacharya United States 11 427 0.8× 81 0.6× 15 0.5× 17 0.7× 15 1.9× 20 445
Makoto Yabuuchi Japan 13 739 1.3× 167 1.2× 44 1.6× 27 1.1× 7 0.9× 59 763
Satyanand Nalam United States 12 435 0.8× 114 0.8× 15 0.5× 12 0.5× 4 0.5× 17 449
Liang-Teck Pang United States 10 431 0.8× 165 1.2× 18 0.6× 50 2.1× 6 0.8× 16 445

Countries citing papers authored by S. Ohbayashi

Since Specialization
Citations

This map shows the geographic impact of S. Ohbayashi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Ohbayashi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Ohbayashi more than expected).

Fields of papers citing papers by S. Ohbayashi

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Ohbayashi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Ohbayashi. The network helps show where S. Ohbayashi may publish in the future.

Co-authorship network of co-authors of S. Ohbayashi

This figure shows the co-authorship network connecting the top 25 collaborators of S. Ohbayashi. A scholar is included among the top collaborators of S. Ohbayashi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Ohbayashi. S. Ohbayashi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Ohbayashi, S., K. Sonoda, Y. Hirano, et al.. (2010). Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis. 95–96. 30 indexed citations
2.
Nii, Koji, Yasumasa Tsukamoto, Makoto Yabuuchi, et al.. (2009). Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. IEEE Journal of Solid-State Circuits. 44(3). 977–986. 36 indexed citations
3.
Yabuuchi, Makoto, Koji Nii, Yasumasa Tsukamoto, et al.. (2008). A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. IEICE technical report. Speech. 108(140). 17–21. 3 indexed citations
4.
Ohbayashi, S., Yasumasa Tsukamoto, Atsushi Ishii, et al.. (2008). A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE Journal of Solid-State Circuits. 43(1). 96–108. 10 indexed citations
5.
Nii, Koji, Makoto Yabuuchi, Yasumasa Tsukamoto, et al.. (2008). A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. 212–213. 89 indexed citations
6.
Nii, Koji, Makoto Yabuuchi, Yasumasa Tsukamoto, et al.. (2008). A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE Journal of Solid-State Circuits. 43(1). 180–191. 49 indexed citations
7.
Yabuuchi, Makoto, Koji Nii, Yasumasa Tsukamoto, et al.. (2007). A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. 326–606. 47 indexed citations
8.
Ohbayashi, S., Makoto Yabuuchi, Koji Nii, et al.. (2007). A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE Journal of Solid-State Circuits. 42(4). 820–829. 103 indexed citations
9.
Yamagami, Y., Naoki Kotani, Koji Nii, et al.. (2007). A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues. 41. 254–255. 11 indexed citations
10.
Ohbayashi, S., Makoto Yabuuchi, Susumu Imaoka, et al.. (2007). A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. 488–617. 4 indexed citations
11.
Yabuuchi, Makoto, S. Ohbayashi, Koji Nii, et al.. (2006). A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits. 106(207). 149–153. 2 indexed citations
12.
Imaoka, Susumu, Koji Nii, Makoto Yabuuchi, et al.. (2006). A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC. IEICE Technical Report; IEICE Tech. Rep.. 106(206). 133–136. 3 indexed citations
13.
Ohbayashi, S., Makoto Yabuuchi, Koji Nii, et al.. (2006). A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits. 17–18. 32 indexed citations
14.
Nii, Koji, Yuichi Masuda, Makoto Yabuuchi, et al.. (2006). A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC. 130–131. 10 indexed citations
15.
Ishibashi, Koichiro, S. Ohbayashi, Yasumasa Tsukamoto, et al.. (2006). Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models. 1–4. 2 indexed citations
16.
17.
Sato, H., T. Wada, S. Ohbayashi, et al.. (1999). A 500-MHz pipelined burst SRAM with improved SER immunity. IEEE Journal of Solid-State Circuits. 34(11). 1571–1579. 21 indexed citations
18.
Wada, T., et al.. (1993). A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. IEEE Journal of Solid-State Circuits. 28(12). 1362–1369. 2 indexed citations
19.
Ohbayashi, S., Satoshi Takano, Keiko Anami, et al.. (1991). A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy. IEEE Journal of Solid-State Circuits. 26(4). 507–512. 13 indexed citations
20.
Ohbayashi, S., Satoshi Takano, Keiko Anami, et al.. (1990). A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy. 41–42. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

Breakdown of academic impact, for papers by Yong-Gee Ng Breakdown of academic impact, for papers by Tomoaki Yabe Breakdown of academic impact, for papers by Y. Yamagami Breakdown of academic impact, for papers by A.J. Bhavnagarwala Breakdown of academic impact, for papers by Y. Takeyama Breakdown of academic impact, for papers by Osamu Hirabayashi Breakdown of academic impact, for papers by Uddalak Bhattacharya Breakdown of academic impact, for papers by Makoto Yabuuchi Breakdown of academic impact, for papers by Satyanand Nalam Breakdown of academic impact, for papers by Liang-Teck Pang
Rankless by CCL
2026