Tomoaki Yabe

445 total citations
23 papers, 330 citations indexed

About

Tomoaki Yabe is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Tomoaki Yabe has authored 23 papers receiving a total of 330 indexed citations (citations by other indexed papers that have themselves been cited), including 23 papers in Electrical and Electronic Engineering, 7 papers in Biomedical Engineering and 4 papers in Hardware and Architecture. Recurrent topics in Tomoaki Yabe's work include Low-power high-performance VLSI design (20 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers) and Semiconductor materials and devices (12 papers). Tomoaki Yabe is often cited by papers focused on Low-power high-performance VLSI design (20 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers) and Semiconductor materials and devices (12 papers). Tomoaki Yabe collaborates with scholars based in Japan and United States. Tomoaki Yabe's co-authors include Y. Takeyama, K. Kushida, Atsushi Kawasumi, Osamu Hirabayashi, Y. Fujimura, Akira Suzuki, Tomoharu Nakazato, Tadahiro Sasaki, T. Sasaki and Koji Imai and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and IEICE Technical Report; IEICE Tech. Rep..

In The Last Decade

Tomoaki Yabe

21 papers receiving 312 citations

Peers

Tomoaki Yabe
Y. Takeyama Japan
Gordon Gammie United States
Osamu Hirabayashi Japan
H. Mair United States
S. Ohbayashi Japan
Y. Yamagami Japan
Christos Vezyrtzis United States
H. Akamatsu Japan
Ming-Chien Tsai Taiwan
T. Noguchi Japan
Y. Takeyama Japan
Tomoaki Yabe
Citations per year, relative to Tomoaki Yabe Tomoaki Yabe (= 1×) peers Y. Takeyama

Countries citing papers authored by Tomoaki Yabe

Since Specialization
Citations

This map shows the geographic impact of Tomoaki Yabe's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tomoaki Yabe with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tomoaki Yabe more than expected).

Fields of papers citing papers by Tomoaki Yabe

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Tomoaki Yabe. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tomoaki Yabe. The network helps show where Tomoaki Yabe may publish in the future.

Co-authorship network of co-authors of Tomoaki Yabe

This figure shows the co-authorship network connecting the top 25 collaborators of Tomoaki Yabe. A scholar is included among the top collaborators of Tomoaki Yabe based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Tomoaki Yabe. Tomoaki Yabe is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Hirabayashi, Osamu, et al.. (2013). A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. IEEE Journal of Solid-State Circuits. 49(1). 118–126. 15 indexed citations
2.
Hirabayashi, Osamu, Y. Takeyama, Atsushi Kawasumi, et al.. (2013). A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. 320–321. 6 indexed citations
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Kawasumi, Atsushi, Y. Takeyama, Osamu Hirabayashi, et al.. (2012). Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. 1–4. 5 indexed citations
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Kawasumi, Atsushi, et al.. (2011). A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. IEEE Journal of Solid-State Circuits. 46(11). 2545–2551. 33 indexed citations
7.
Hirabayashi, Osamu, et al.. (2010). A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS. IEICE Technical Report; IEICE Tech. Rep.. 110(9). 1–6. 2 indexed citations
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Hirabayashi, Osamu, et al.. (2009). A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver. IEICE Technical Report; IEICE Tech. Rep.. 109(2). 21–26. 7 indexed citations
10.
Hirabayashi, Osamu, Atsushi Kawasumi, Akira Suzuki, et al.. (2009). A process-variation-tolerant dual-power-supply SRAM with 0.179&#x00B5;m<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver. 458–459,459a. 73 indexed citations
11.
Kawasumi, Atsushi, et al.. (2009). A low supply voltage operation SRAM with HCI trimmed sense amplifiers. 221–224. 4 indexed citations
12.
Kushida, K., et al.. (2009). A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme. IEEE Journal of Solid-State Circuits. 44(4). 1192–1198. 44 indexed citations
13.
Kawasumi, Atsushi, et al.. (2008). A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell. IEICE Technical Report; IEICE Tech. Rep.. 108(6). 1–6. 1 indexed citations
14.
Kawasumi, Atsushi, Tomoaki Yabe, Y. Takeyama, et al.. (2008). A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell. 382–622. 29 indexed citations
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Hirabayashi, Osamu, Akira Suzuki, Tomoaki Yabe, et al.. (2003). DFT techniques for wafer-level at-speed testing of high-speed SRAMs. 164–169. 3 indexed citations
19.
Takeuchi, Hiroaki, et al.. (2002). A DRAM module generator with an expandable cell array scheme. 287–290.
20.
Kakumu, M., M. Kinugawa, Hiroaki Takeuchi, et al.. (1990). A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell. IEEE Journal of Solid-State Circuits. 25(5). 1082–1092. 11 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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