Y. Takeyama

584 total citations
27 papers, 399 citations indexed

About

Y. Takeyama is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Y. Takeyama has authored 27 papers receiving a total of 399 indexed citations (citations by other indexed papers that have themselves been cited), including 27 papers in Electrical and Electronic Engineering, 7 papers in Hardware and Architecture and 5 papers in Biomedical Engineering. Recurrent topics in Y. Takeyama's work include Low-power high-performance VLSI design (24 papers), Advancements in Semiconductor Devices and Circuit Design (18 papers) and Semiconductor materials and devices (15 papers). Y. Takeyama is often cited by papers focused on Low-power high-performance VLSI design (24 papers), Advancements in Semiconductor Devices and Circuit Design (18 papers) and Semiconductor materials and devices (15 papers). Y. Takeyama collaborates with scholars based in Japan. Y. Takeyama's co-authors include K. Kushida, Osamu Hirabayashi, Tomoaki Yabe, Atsushi Kawasumi, Y. Fujimura, Akira Suzuki, Hiroyuki Otake, Tomoharu Nakazato, Tadahiro Sasaki and T. Sasaki and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and IEICE Technical Report; IEICE Tech. Rep..

In The Last Decade

Y. Takeyama

26 papers receiving 377 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Y. Takeyama Japan 12 389 86 45 22 11 27 399
Tomoaki Yabe Japan 11 320 0.8× 79 0.9× 44 1.0× 18 0.8× 11 1.0× 23 330
Osamu Hirabayashi Japan 10 333 0.9× 81 0.9× 43 1.0× 19 0.9× 7 0.6× 25 340
H. Mair United States 5 256 0.7× 87 1.0× 93 2.1× 37 1.7× 8 0.7× 7 280
S. Ohbayashi Japan 12 564 1.4× 141 1.6× 24 0.5× 28 1.3× 6 0.5× 27 582
Kazumasa Yanagisawa Japan 13 689 1.8× 167 1.9× 121 2.7× 43 2.0× 7 0.6× 33 715
Tuyet Nguyen United States 7 434 1.1× 200 2.3× 84 1.9× 54 2.5× 6 0.5× 10 469
S. Bobba United States 10 373 1.0× 150 1.7× 46 1.0× 23 1.0× 3 0.3× 19 389
C.H. Kim United States 13 732 1.9× 189 2.2× 80 1.8× 48 2.2× 4 0.4× 16 755
Ming-Chien Tsai Taiwan 6 313 0.8× 95 1.1× 31 0.7× 7 0.3× 7 0.6× 11 325
Christos Vezyrtzis United States 6 132 0.3× 45 0.5× 70 1.6× 15 0.7× 8 0.7× 14 161

Countries citing papers authored by Y. Takeyama

Since Specialization
Citations

This map shows the geographic impact of Y. Takeyama's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y. Takeyama with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y. Takeyama more than expected).

Fields of papers citing papers by Y. Takeyama

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Y. Takeyama. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y. Takeyama. The network helps show where Y. Takeyama may publish in the future.

Co-authorship network of co-authors of Y. Takeyama

This figure shows the co-authorship network connecting the top 25 collaborators of Y. Takeyama. A scholar is included among the top collaborators of Y. Takeyama based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y. Takeyama. Y. Takeyama is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Takeyama, Y., et al.. (2014). A 7ns-Access-Time 25μW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current. IEICE Technical Report; IEICE Tech. Rep.. 114(13). 59–64. 1 indexed citations
2.
Hirabayashi, Osamu, et al.. (2013). A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. IEEE Journal of Solid-State Circuits. 49(1). 118–126. 15 indexed citations
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Kawasumi, Atsushi, Y. Takeyama, Osamu Hirabayashi, et al.. (2012). Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. 1–4. 5 indexed citations
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Kawasumi, Atsushi, et al.. (2011). A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. IEEE Journal of Solid-State Circuits. 46(11). 2545–2551. 33 indexed citations
7.
Hirabayashi, Osamu, et al.. (2010). A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS. IEICE Technical Report; IEICE Tech. Rep.. 110(9). 1–6. 2 indexed citations
8.
9.
Hirabayashi, Osamu, et al.. (2009). A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver. IEICE Technical Report; IEICE Tech. Rep.. 109(2). 21–26. 7 indexed citations
10.
Hirabayashi, Osamu, Atsushi Kawasumi, Akira Suzuki, et al.. (2009). A process-variation-tolerant dual-power-supply SRAM with 0.179&#x00B5;m<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver. 458–459,459a. 73 indexed citations
11.
Kawasumi, Atsushi, et al.. (2009). A low supply voltage operation SRAM with HCI trimmed sense amplifiers. 221–224. 4 indexed citations
12.
Kawasumi, Atsushi, et al.. (2008). A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell. IEICE Technical Report; IEICE Tech. Rep.. 108(6). 1–6. 1 indexed citations
13.
Kawasumi, Atsushi, Tomoaki Yabe, Y. Takeyama, et al.. (2008). A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell. 382–622. 29 indexed citations
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Takeyama, Y., et al.. (2006). A Low Leakage SRAM Macro With Replica Cell Biasing Scheme. IEEE Journal of Solid-State Circuits. 41(4). 815–822. 28 indexed citations
17.
Kawasaki, Hikaru, K. Okano, A. Kaneko, et al.. (2006). Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond. 70–71. 34 indexed citations
18.
Takeyama, Y., et al.. (2005). A low leakage SRAM macro with replica cell biasing scheme. 166–167. 9 indexed citations
19.
Hirabayashi, Osamu, Akira Suzuki, Tomoaki Yabe, et al.. (2003). DFT techniques for wafer-level at-speed testing of high-speed SRAMs. 164–169. 3 indexed citations
20.
Kawasumi, Atsushi, et al.. (2002). Bus architecture for 600-MHz 4.5-Mb DDR SRAM. 178–179. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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