H. Akamatsu

575 total citations
22 papers, 420 citations indexed

About

H. Akamatsu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, H. Akamatsu has authored 22 papers receiving a total of 420 indexed citations (citations by other indexed papers that have themselves been cited), including 21 papers in Electrical and Electronic Engineering, 6 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in H. Akamatsu's work include Low-power high-performance VLSI design (16 papers), Advancements in Semiconductor Devices and Circuit Design (13 papers) and Semiconductor materials and devices (13 papers). H. Akamatsu is often cited by papers focused on Low-power high-performance VLSI design (16 papers), Advancements in Semiconductor Devices and Circuit Design (13 papers) and Semiconductor materials and devices (13 papers). H. Akamatsu collaborates with scholars based in Japan and United States. H. Akamatsu's co-authors include H. Yamauchi, Y. Yamagami, Tsutomu Fujita, Toshikazu Suzuki, Akira Matsuzawa, T. Oashi, Yasumasa Tsukamoto, Makoto Yabuuchi, Koji Nii and S. Ohbayashi and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEICE Transactions on Electronics.

In The Last Decade

H. Akamatsu

22 papers receiving 399 citations

Peers

H. Akamatsu
Osamu Hirabayashi Japan
Y. Takeyama Japan
Tomoaki Yabe Japan
S. Ohbayashi Japan
Ku He United States
Y. Yamagami Japan
K. Heragu United States
Martin Saint-Laurent United States
Simone Erba Italy
Hùng Ngô United States
Osamu Hirabayashi Japan
H. Akamatsu
Citations per year, relative to H. Akamatsu H. Akamatsu (= 1×) peers Osamu Hirabayashi

Countries citing papers authored by H. Akamatsu

Since Specialization
Citations

This map shows the geographic impact of H. Akamatsu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by H. Akamatsu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites H. Akamatsu more than expected).

Fields of papers citing papers by H. Akamatsu

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by H. Akamatsu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by H. Akamatsu. The network helps show where H. Akamatsu may publish in the future.

Co-authorship network of co-authors of H. Akamatsu

This figure shows the co-authorship network connecting the top 25 collaborators of H. Akamatsu. A scholar is included among the top collaborators of H. Akamatsu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with H. Akamatsu. H. Akamatsu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Yabuuchi, Makoto, Koji Nii, Yasumasa Tsukamoto, et al.. (2008). A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. IEICE technical report. Speech. 108(140). 17–21. 3 indexed citations
2.
Suzuki, Toshikazu, et al.. (2008). A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. IEEE Journal of Solid-State Circuits. 43(9). 2109–2119. 70 indexed citations
3.
Nii, Koji, Makoto Yabuuchi, Yasumasa Tsukamoto, et al.. (2008). A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE Journal of Solid-State Circuits. 43(1). 180–191. 49 indexed citations
4.
Yamagami, Y., Naoki Kotani, Koji Nii, et al.. (2008). A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE Journal of Solid-State Circuits. 43(4). 938–945. 34 indexed citations
5.
6.
Yabuuchi, Makoto, Koji Nii, Yasumasa Tsukamoto, et al.. (2007). A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. 326–606. 47 indexed citations
7.
Yamagami, Y., Naoki Kotani, Koji Nii, et al.. (2007). A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues. 41. 254–255. 11 indexed citations
8.
Suzuki, Tetsuya, et al.. (2006). A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses. 11–12. 20 indexed citations
9.
Yamauchi, H., H. Akamatsu, & Tsutomu Fujita. (2005). A Low Power Complete Charge-Recycling Bus Architecture for Ultra-High Data Rate Ulsi's. sc 28. 21–22. 1 indexed citations
10.
Yamauchi, H., et al.. (2002). Gate-over-driving CMOS architecture for 0.5 V single-power-supply-operated devices. 290–291,. 5 indexed citations
11.
12.
13.
Akamatsu, H.. (1997). A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs. IEICE Transactions on Electronics. 80(12). 1572–1577. 8 indexed citations
14.
Yamauchi, H., et al.. (1997). A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 5(4). 377–387. 8 indexed citations
15.
16.
Yamauchi, H., H. Akamatsu, & Tsutomu Fujita. (1995). A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's. IEICE Transactions on Electronics. 78(4). 394–403. 3 indexed citations
17.
Yamauchi, H., H. Akamatsu, & Tsutomu Fujita. (1995). An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. IEEE Journal of Solid-State Circuits. 30(4). 423–431. 60 indexed citations
18.
Akamatsu, H., Y. Naito, Toshiaki Tsuji, et al.. (1994). A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures. IEEE Journal of Solid-State Circuits. 29(11). 1310–1316. 4 indexed citations
19.
Akamatsu, H., et al.. (1990). A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier. IEEE Journal of Solid-State Circuits. 25(1). 30–35. 3 indexed citations
20.
Inoue, Masasi, T. Yamada, H. Yamauchi, et al.. (1988). A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture. IEEE Journal of Solid-State Circuits. 23(5). 1104–1112. 23 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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