Y. Hirano

435 citations

30 papers · 319 indexed · h-index 11

Co-authors: J. R. Selman Isamu Uchida Said Al Hallaj T. Iwamatsu T. Ohmi Hiroyuki Shimada T. Ippōshi S. Maegawa
Topics: Advancements in Semiconductor Devices and Circuit Design (24 papers)Semiconductor materials and devices (22 papers)Integrated Circuits and Semiconductor Failure Analysis (7 papers)
Cited by: Automotive Engineering Electrical and Electronic Engineering Hardware and Architecture
Journals: Journal of Power Sources IEEE Transactions on Electron Devices Japanese Journal of Applied Physics
Partner nations: Japan United States Germany

In The Last Decade

Y. Hirano

27 papers receiving 297 citations

Peers

Countries citing papers authored by Y. Hirano

Since Specialization

Citations

This map shows the geographic impact of Y. Hirano's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y. Hirano with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y. Hirano more than expected).

Fields of papers citing papers by Y. Hirano

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Y. Hirano. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y. Hirano. The network helps show where Y. Hirano may publish in the future.

Co-authorship network of co-authors of Y. Hirano

This figure shows the co-authorship network connecting the top 25 collaborators of Y. Hirano. A scholar is included among the top collaborators of Y. Hirano based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y. Hirano. Y. Hirano is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis 2010 ·(unknown),S. Ohbayashi,(unknown),K. Sonoda,(unknown),Y. Hirano,K. Ishikawa,O. Tsuchiya,Y. Inoue	30
2	A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices 2007 ·Y. Hirano,(unknown),(unknown),Hirofumi Shinohara,Takashi Terada,(unknown),T. Iwamatsu,(unknown),Tetsuya Uchida,(unknown),Koji Nii,Yasumasa Tsukamoto,Makoto Yabuuchi,T. Ippōshi,H. Oda,Yasuo Inoue	6
3	Impact of Body Bias Controlling in Partially Depleted SOI Devices with Hybrid Trench Isolation Technology 2005 ·T. Iwamatsu,(unknown),Y. Hirano,Tatsuhiko N. Ikeda,(unknown),T. Ippōshi,(unknown),Yuzuru Ohji	1
4	Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application 2004 ·Y. Hirano,T. Ippōshi,Hung Dang,Takuma Matsumoto,T. Iwamatsu,Koji Nii,Yasumasa Tsukamoto,(unknown),Hiromitsu Kato,S. Maegawa,Kazutami Arimoto,Y. Inoue,M. Inuishi,Yuzuru Ohji	16
5	Evaluation of Mobile Ethernet switch on network processor 2004 ·Akira Ōkubo,(unknown),Y. Hirano,(unknown),Masahiro Kuroda	2
6	A 400MHz 183mW microcontroller in body-tied SOI technology 2003 ·H. Sato,(unknown),Koji Nii,Kōji Yoshida,Y. Nakase,Hiroshi Makino,Akira Yamada,(unknown),(unknown),Y. Hirano,T. Ippōshi	1
7	Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI) 2003 ·Y. Hirano,S. Maeda,Takuji Matsumoto,Koji Nii,T. Iwamatsu,Yasuo Yamaguchi,T. Ippōshi,Hiroshi Kawashima,S. Maegawa,M. Inuishi,T. Nishimura	1
8	Novel SOI wafer engineering using low stress and high mobility CMOSFET with >100<-channel for embedded RF/analog applications 2003 ·(unknown),S. Maeda,Hung Dang,Taro Uchida,K. Ota,Y. Hirano,(unknown),T. Iwamatsu,T. Ippōshi,H. Oda,S. Maegawa,Yuichi Inoue,T. Nishimura	18
9	70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications 2002 ·(unknown),Shoji Maeda,Kosuke Ota,Y. Hirano,(unknown),(unknown),T. Iwamatsu,(unknown),(unknown),Yutaro Yamaguchi,T. Ippōshi,H. Oda,S. Maegawa,Y. Inoue,M. Inuishi	12
10	Tantalum-gate SOI MOSFET's featuring excellent threshold voltage control in low-power applications 2002 ·Hiroyuki Shimada,(unknown),Y. Hirano,T. Ohmi	2
11	Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology 2002 ·Y. Hirano,Takuji Matsumoto,Satoshi Maeda,T. Iwamatsu,T. Kunikiyo,Koji Nii,(unknown),Yutaro Yamaguchi,T. Ippōshi,S. Maegawa,M. Inuishi	17
12	Threshold voltage adjustment in SOI MOSFETs by employing tantalum for gate material 2002 ·Hiroyuki Shimada,Y. Hirano,(unknown),T. Ohmi	3
13	Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications 2002 ·S. Maeda,(unknown),(unknown),(unknown),Takuji Matsumoto,Y. Hirano,T. Iwamatsu,Yutaro Yamaguchi,T. Ippōshi,(unknown),K. Mashiko,S. Maegawa,M. Inuishi	6
14	Reliable tantalum gate fully-depleted-SOI MOSFETs with 0.15 μm gate length by low-temperature processing below 500°C 2002 ·(unknown),(unknown),Y. Hirano,Hiroyuki Shimada,Mizuho Morita,T. Ohmi	0
15	Cooperative research on safety fundamentals of lithium batteries 2001 ·Journal of Power Sources ·J. R. Selman,Said Al Hallaj,Isamu Uchida,Y. Hirano	81
16	Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications 2001 ·IEEE Transactions on Electron Devices ·S. Maeda,(unknown),Kazuya Yamamoto,(unknown),Takuji Matsumoto,Y. Hirano,T. Iwamatsu,Yutaro Yamaguchi,T. Ippōshi,(unknown),K. Mashiko,S. Maegawa,M. Inuishi	13
17	Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI) 2001 ·IEEE Transactions on Electron Devices ·Y. Hirano,S. Maeda,Takuji Matsumoto,Koji Nii,T. Iwamatsu,Yasuo Yamaguchi,T. Ippōshi,Hiroshi Kawashima,S. Maegawa,M. Inuishi,T. Nishimura	4
18	Active body-bias SOI-CMOS driver circuits 1997 ·(unknown),(unknown),(unknown),Y. Hirano,(unknown),(unknown)	3
19	Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications 1997 ·IEEE Transactions on Electron Devices ·Hiroyuki Shimada,Y. Hirano,(unknown),(unknown),T. Ohmi	27
20	Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing 1997 ·IEEE Transactions on Electron Devices ·(unknown),(unknown),Y. Hirano,Hiroyuki Shimada,Mizuho Morita,T. Ohmi	23

About Y. Hirano

Y. Hirano is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Statistics, Probability and Uncertainty, having authored 30 papers that have together received 319 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (24 papers), Semiconductor materials and devices (22 papers) and Integrated Circuits and Semiconductor Failure Analysis (7 papers). The work is most often cited by research in Automotive Engineering (74 citations), Electrical and Electronic Engineering (308 citations) and Hardware and Architecture (14 citations). Y. Hirano has collaborated with scholars based in Japan, United States and Germany. Frequent co-authors include J. R. Selman, Isamu Uchida, Said Al Hallaj, T. Iwamatsu, T. Ohmi, Hiroyuki Shimada, T. Ippōshi, S. Maegawa, Koji Nii and Yutaro Yamaguchi. Their work appears in journals such as Journal of Power Sources, IEEE Transactions on Electron Devices and Japanese Journal of Applied Physics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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