Y. Yamagami

491 citations

17 papers · 353 indexed · h-index 9

Co-authors: H. Akamatsu H. Yamauchi Koji Nii Yasumasa Tsukamoto Hiroshi Makino Susumu Imaoka Toshikazu Suzuki A. Shibayama
Topics: Advancements in Semiconductor Devices and Circuit Design (15 papers)Low-power high-performance VLSI design (13 papers)Semiconductor materials and devices (12 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Computer Networks and Communications
Journals: IEEE Journal of Solid-State Circuits IEICE Transactions on Electronics IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
Partner nations: Japan United States

In The Last Decade

Y. Yamagami

15 papers receiving 335 citations

Peers

Countries citing papers authored by Y. Yamagami

Since Specialization

Citations

This map shows the geographic impact of Y. Yamagami's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y. Yamagami with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y. Yamagami more than expected).

Fields of papers citing papers by Y. Yamagami

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Y. Yamagami. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y. Yamagami. The network helps show where Y. Yamagami may publish in the future.

Co-authorship network of co-authors of Y. Yamagami

This figure shows the co-authorship network connecting the top 25 collaborators of Y. Yamagami. A scholar is included among the top collaborators of Y. Yamagami based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y. Yamagami. Y. Yamagami is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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17 of 17 papers shown

#	Work	Indexed citations
1	A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations 2008 ·IEICE technical report. Speech ·Makoto Yabuuchi,Koji Nii,Yasumasa Tsukamoto,S. Ohbayashi,Susumu Imaoka,Y. Yamagami,(unknown),(unknown),(unknown),H. Akamatsu,Hirofumi Shinohara	3
2	A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses 2008 ·IEEE Journal of Solid-State Circuits ·Toshikazu Suzuki,H. Yamauchi,Y. Yamagami,(unknown),H. Akamatsu	70
3	A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations 2008 ·IEEE Journal of Solid-State Circuits ·Koji Nii,Makoto Yabuuchi,Yasumasa Tsukamoto,S. Ohbayashi,Susumu Imaoka,Hiroshi Makino,Y. Yamagami,(unknown),(unknown),T. Oashi,Keiji Hashimoto,(unknown),(unknown),(unknown),H. Akamatsu,Hirofumi Shinohara	49
4	Sensitivity Analysis and Optimization Algorithm --- Based on Nonlinear Programming --- 2008 ·IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ·Masayuki Oda,Y. Yamagami,(unknown),Yoshifumi Nishio,Akio Ushida	0
5	A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues 2008 ·IEEE Journal of Solid-State Circuits ·(unknown),(unknown),(unknown),Y. Yamagami,Naoki Kotani,(unknown),Koji Nii,Makoto Yabuuchi,Yasumasa Tsukamoto,S. Ohbayashi,T. Oashi,Hiroshi Makino,Hirofumi Shinohara,H. Akamatsu	34
6	A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations 2007 ·Makoto Yabuuchi,Koji Nii,Yasumasa Tsukamoto,S. Ohbayashi,Susumu Imaoka,Hiroshi Makino,Y. Yamagami,(unknown),(unknown),T. Oashi,Keiji Hashimoto,(unknown),(unknown),(unknown),H. Akamatsu,Hirofumi Shinohara	47
7	A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses 2007 ·IEICE Transactions on Electronics ·H. Yamauchi,(unknown),Y. Yamagami	7
8	A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues 2007 ·(unknown),(unknown),(unknown),Y. Yamagami,Naoki Kotani,(unknown),Koji Nii,Makoto Yabuuchi,Yasumasa Tsukamoto,S. Ohbayashi,T. Oashi,Hiroshi Makino,Hirofumi Shinohara,H. Akamatsu	11
9	Spice-Oriented Frequency-Domain Analysis of Nonlinear Electronic Circuits 2007 ·IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ·(unknown),Yasutaka Taniguchi,Masayuki Oda,Y. Yamagami,Yoshifumi Nishio,Akio Ushida	1
10	A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses 2006 ·Tetsuya Suzuki,H. Yamauchi,Y. Yamagami,(unknown),H. Akamatsu	20
11	A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation 2006 ·IEICE Transactions on Electronics ·H. Yamauchi,T. Suzuki,Y. Yamagami	3
12	A Sub-0.5-V Operating Embedded SRAM Featuring a Multi-Bit-Error-Immune Hidden-ECC Scheme 2005 ·IEEE Journal of Solid-State Circuits ·T. Suzuki,Y. Yamagami,(unknown),A. Shibayama,H. Akamatsu,H. Yamauchi	23
13	0.3 to 1.5V embedded SRAM with device-fluctuation-tolerant access-control and cosmic-ray-immune hidden-ECC scheme 2005 ·T. Suzuki,Y. Yamagami,(unknown),A. Shibayama,H. Akamatsu,H. Yamauchi	7
14	A 90 nm low power 32 K-byte embedded SRAM with gate leakage suppression circuit for mobile applications 2004 ·Koji Nii,(unknown),(unknown),Susumu Imaoka,Yasumasa Tsukamoto,Y. Yamagami,Tetsuya Suzuki,A. Shibayama,Hiroshi Makino,(unknown)	23
15	A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications 2004 ·IEEE Journal of Solid-State Circuits ·Koji Nii,Yasumasa Tsukamoto,(unknown),Susumu Imaoka,Y. Yamagami,Tetsuya Suzuki,A. Shibayama,Hiroshi Makino,(unknown)	52
16	Comparison of the Interconnect Capacitances of Various SRAM Cell Layouts To Achieve High Speed, Low Power SRAM Cells 2003 ·Yasumasa Tsukamoto,Koji Nii,Y. Yamagami,(unknown),Susumu Imaoka,(unknown),A. Shibayama,Hiroshi Makino	2
17	Analysis of LSI Circuits Coupled with RCG Interconnects-Asymptotic Method 2002 ·ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ·Akio Ushida,H Sakaguchi,Y. Yamagami,Yoshifumi Nishio	1

About Y. Yamagami

Y. Yamagami is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Statistical and Nonlinear Physics, having authored 17 papers that have together received 353 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (15 papers), Low-power high-performance VLSI design (13 papers) and Semiconductor materials and devices (12 papers). The work is most often cited by research in Hardware and Architecture (93 citations), Electrical and Electronic Engineering (350 citations) and Computer Networks and Communications (13 citations). Y. Yamagami has collaborated with scholars based in Japan and United States. Frequent co-authors include H. Akamatsu, H. Yamauchi, Koji Nii, Yasumasa Tsukamoto, Hiroshi Makino, Susumu Imaoka, Toshikazu Suzuki, A. Shibayama, Tetsuya Suzuki and Makoto Yabuuchi. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEICE Transactions on Electronics and IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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