Y. Yamagami

491 total citations
17 papers, 353 citations indexed

About

Y. Yamagami is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Y. Yamagami has authored 17 papers receiving a total of 353 indexed citations (citations by other indexed papers that have themselves been cited), including 16 papers in Electrical and Electronic Engineering, 3 papers in Hardware and Architecture and 2 papers in Biomedical Engineering. Recurrent topics in Y. Yamagami's work include Advancements in Semiconductor Devices and Circuit Design (15 papers), Low-power high-performance VLSI design (13 papers) and Semiconductor materials and devices (12 papers). Y. Yamagami is often cited by papers focused on Advancements in Semiconductor Devices and Circuit Design (15 papers), Low-power high-performance VLSI design (13 papers) and Semiconductor materials and devices (12 papers). Y. Yamagami collaborates with scholars based in Japan and United States. Y. Yamagami's co-authors include H. Akamatsu, H. Yamauchi, Yasumasa Tsukamoto, Hiroshi Makino, Koji Nii, Susumu Imaoka, Toshikazu Suzuki, A. Shibayama, Tetsuya Suzuki and S. Ohbayashi and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEICE Transactions on Electronics and IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

In The Last Decade

Y. Yamagami

15 papers receiving 335 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Y. Yamagami Japan 9 350 93 14 13 5 17 353
Osamu Hirabayashi Japan 10 333 1.0× 81 0.9× 43 3.1× 19 1.5× 7 1.4× 25 340
S. Ohbayashi Japan 12 564 1.6× 141 1.5× 24 1.7× 28 2.2× 6 1.2× 27 582
Ming-Chien Tsai Taiwan 6 313 0.9× 95 1.0× 31 2.2× 7 0.5× 7 1.4× 11 325
Satyanand Nalam United States 12 435 1.2× 114 1.2× 12 0.9× 15 1.2× 5 1.0× 17 449
Tomoaki Yabe Japan 11 320 0.9× 79 0.8× 44 3.1× 18 1.4× 11 2.2× 23 330
H. Akamatsu Japan 11 413 1.2× 105 1.1× 37 2.6× 32 2.5× 5 1.0× 22 420
Y. Takeyama Japan 12 389 1.1× 86 0.9× 45 3.2× 22 1.7× 11 2.2× 27 399
R. Houle United States 8 272 0.8× 77 0.8× 14 1.0× 21 1.6× 2 0.4× 14 286
J.J. Liaw Taiwan 8 250 0.7× 49 0.5× 20 1.4× 13 1.0× 3 0.6× 14 256
Ku He United States 9 323 0.9× 82 0.9× 30 2.1× 15 1.2× 4 0.8× 14 335

Countries citing papers authored by Y. Yamagami

Since Specialization
Citations

This map shows the geographic impact of Y. Yamagami's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y. Yamagami with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y. Yamagami more than expected).

Fields of papers citing papers by Y. Yamagami

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Y. Yamagami. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y. Yamagami. The network helps show where Y. Yamagami may publish in the future.

Co-authorship network of co-authors of Y. Yamagami

This figure shows the co-authorship network connecting the top 25 collaborators of Y. Yamagami. A scholar is included among the top collaborators of Y. Yamagami based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y. Yamagami. Y. Yamagami is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

17 of 17 papers shown
1.
Yabuuchi, Makoto, Koji Nii, Yasumasa Tsukamoto, et al.. (2008). A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. IEICE technical report. Speech. 108(140). 17–21. 3 indexed citations
2.
Nii, Koji, Makoto Yabuuchi, Yasumasa Tsukamoto, et al.. (2008). A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE Journal of Solid-State Circuits. 43(1). 180–191. 49 indexed citations
3.
Yamagami, Y., Naoki Kotani, Koji Nii, et al.. (2008). A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE Journal of Solid-State Circuits. 43(4). 938–945. 34 indexed citations
4.
Suzuki, Toshikazu, et al.. (2008). A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. IEEE Journal of Solid-State Circuits. 43(9). 2109–2119. 70 indexed citations
5.
Oda, Masayuki, et al.. (2008). Sensitivity Analysis and Optimization Algorithm --- Based on Nonlinear Programming ---. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. E91-A(9). 2426–2434.
6.
Yabuuchi, Makoto, Koji Nii, Yasumasa Tsukamoto, et al.. (2007). A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. 326–606. 47 indexed citations
7.
Yamauchi, H., et al.. (2007). A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Transactions on Electronics. E90-C(4). 749–757. 7 indexed citations
8.
Yamagami, Y., Naoki Kotani, Koji Nii, et al.. (2007). A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues. 41. 254–255. 11 indexed citations
9.
Taniguchi, Yasutaka, et al.. (2007). Spice-Oriented Frequency-Domain Analysis of Nonlinear Electronic Circuits. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. E90-A(2). 406–410. 1 indexed citations
10.
Suzuki, Tetsuya, et al.. (2006). A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses. 11–12. 20 indexed citations
11.
Yamauchi, H., T. Suzuki, & Y. Yamagami. (2006). A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation. IEICE Transactions on Electronics. E89-C(11). 1526–1534. 3 indexed citations
12.
13.
Suzuki, T., et al.. (2005). A Sub-0.5-V Operating Embedded SRAM Featuring a Multi-Bit-Error-Immune Hidden-ECC Scheme. IEEE Journal of Solid-State Circuits. 41(1). 152–160. 23 indexed citations
14.
Nii, Koji, Susumu Imaoka, Yasumasa Tsukamoto, et al.. (2004). A 90 nm low power 32 K-byte embedded SRAM with gate leakage suppression circuit for mobile applications. 247–250. 23 indexed citations
15.
Nii, Koji, Yasumasa Tsukamoto, Susumu Imaoka, et al.. (2004). A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications. IEEE Journal of Solid-State Circuits. 39(4). 684–693. 52 indexed citations
16.
Tsukamoto, Yasumasa, Koji Nii, Y. Yamagami, et al.. (2003). Comparison of the Interconnect Capacitances of Various SRAM Cell Layouts To Achieve High Speed, Low Power SRAM Cells. 2 indexed citations
17.
Ushida, Akio, H Sakaguchi, Y. Yamagami, & Yoshifumi Nishio. (2002). Analysis of LSI Circuits Coupled with RCG Interconnects-Asymptotic Method. ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications. 71–74. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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