M. Assous

699 citations

45 papers · 433 indexed · h-index 14

Impact in

Electronic, Optical and Magnetic Materials
- Copper Interconnects and Reliability
Electrical and Electronic Engineering top 10%
- 3D IC and TSV technologies
- Semiconductor materials and devices
- Electronic Packaging and Soldering Technologies
- Integrated Circuits and Semiconductor Failure Analysis

Papers in ⓘ

Electrical and Electronic Engineering 43
- 3D IC and TSV technologies 28
- Electronic Packaging and Soldering Technologies 20
- Semiconductor materials and devices 13
- Advancements in Semiconductor Devices and Circuit Design 4
- Semiconductor Lasers and Optical Devices 4
- Photonic and Optical Devices 4
Electronic, Optical and Magnetic Materials 20
- Copper Interconnects and Reliability 20

Co-authors: A. Farcy (7 shared papers)R. Blanc (4 shared papers)D. Louis (6 shared papers)Jean Charbonnier (10 shared papers)S. Borel (7 shared papers)L. Arnaud (4 shared papers)H. Feldis (9 shared papers)O. Louveau (5 shared papers)
Journals: Microelectronic Engineering (9 papers)MRS Communications (1 paper)Applied Spectroscopy (1 paper)IEEE Transactions on Device and Materials Reliability (1 paper)SPIRE - Sciences Po Institutional REpository (5 papers)
Partner nations: France Japan Switzerland

In The Last Decade

M. Assous

43 papers receiving 416 citations

Peers

Countries citing papers authored by M. Assous

Since Specialization

Citations

This map shows the geographic impact of M. Assous's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Assous with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Assous more than expected).

Fields of papers citing papers by M. Assous

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. Assous. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Assous. The network helps show where M. Assous may publish in the future.

Co-authors

The 25 scholars most cited alongside M. Assous, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with M. Assous Line = papers co-authored together M. Assous links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 45 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Investigation on TSV impact on 65nm CMOS devices and circuits H. Chaabouni, Maxime Rousseau, Philip R. LeDuc, A. Farcy, R. El Farhane, Aurélie Thuaire, G. Haury, Alexandre Valentian, G. Billiot, M. Assous, F. de Crécy, J. Cluzel, A. Toffoli, D. Bouchu, L. Cadix, T. Lacrevaz, P. Ancey, N. Sillon, B. Fléchet	2010	41
2	Etch mechanisms of low dielectric constant polymers in high density plasmas: Impact of charging effects on profile distortion during the etching process Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena ·D. Fuard, O. Joubert, L. Vallier, M. Assous, P. Berruyer, R. Blanc	2001	32
3	Warpage control of silicon interposer for 2.5D package application Kei Murayama, Mitsuhiro Aizawa, K. Hara, Masahiro Sunohara, Ken Miyairi, Kenichi Mori, Jean Charbonnier, M. Assous, Jean-Philippe Bally, Gilles Simon, Mitsutoshi Higashi	2013	32
4	POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems HAL (Le Centre pour la Communication Scientifique Directe) ·Yvain Thonnart, Stéphane Bernabé, Jean Charbonnier, Christian Bernard, David Coriat, César Fuguet, Pierre Tissier, Benoı̂t Charbonnier, Stéphane Malhouitre, D. Saint-Patrice, M. Assous, Aditya Narayan, Ayse K. Coskun, Denis Dutoit, Pascal Vivet	2020	27
5	Three-dimensional hybrid bonding integration challenges and solutions toward multi-wafer stacking MRS Communications ·L. Arnaud, C. Karam, N. Bresson, Christophe Dubarry, S. Borel, M. Assous, Gaëlle Mauguen, Frank Fournel, M. Gottardi, Thierry Mourier, S. Chéramy, Florence Servant	2020	24
6	Integration of Cu/SiOC in Cu dual damascene interconnect for 0.1-μm technology Microelectronic Engineering ·M. Fayolle, J. Torrès, G. Passemard, Florence Fusalba, Gilles L. Fanget, D. Louis, M. Assous, O. Louveau, M. Rivoire, K. Haxaire, M Mourier, S. Maı̂trejean, P. Besson, Lucile Broussous, L. Arnaud, H. Feldis	2002	23
7	First integration of Cu TSV using die-to-wafer direct bonding and planarization Patrick Leduc, M. Assous, L. Di Cioccio, Marc Zussy, Thomas Signamarcheix, A. Roman, Maxime Rousseau, S. Verrun, Laurent Bally, D. Bouchu, L. Cadix, A. Farcy, N. Sillon	2009	20
8	Impact of patterning and ashing on electrical properties and reliability of interconnects in a porous SiOCH ultra low-k dielectric material Microelectronic Engineering ·M. Aimadeddine, V. Arnal, A. Farcy, C. Guedj, T. Chevolleau, N. Possémé, David Tormey, M. Assous, O. Louveau, F. Volpi, Jose Luis Chavez Torres	2005	20
9	RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking Microelectronic Engineering ·L. Cadix, C. Bermond, C. Fuchs, A. Farcy, Philip R. LeDuc, L. DiCioccio, M. Assous, Maxime Rousseau, F. Lorut, Laurent Chapelon, B. Fléchet, N. Sillon, P. Ancey	2009	19
10	Integration of copper with an organic low-k dielectric in 0.12-μm node interconnect Microelectronic Engineering ·M. Fayolle, G. Passemard, M. Assous, D. Louis, Alessio Beverina, Y. Gobil, J. Cluzel, L. Arnaud	2002	18
11	An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling L. Di Cioccio, Pierric Gueguen, R. Taïbi, Thomas Signamarcheix, Laurent Bally, L. Vandroux, Marc Zussy, S. Verrun, J. Dechamp, Patrick Leduc, M. Assous, D. Bouchu, F. de Crécy, L.L. Chapelon, L. Clavelier	2009	16
12	A new damascene architecture for high-performance metal–insulator–metal capacitors integration Microelectronic Engineering ·A. Farcy, J. Torrès, V. Arnal, M. Fayolle, H. Feldis, Fabrice Jourdan, M. Assous, J.L. Di Maria, V. Vidal	2003	15
13	Challenge of ashing and cleaning on SiOC-H dielectric: characterization and main issues Microelectronic Engineering ·O. Louveau, D. Louis, M. Assous, R. Blanc, P. Brun, S. Lamy, E. Lajoinie	2002	15
14	32nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3 Microelectronic Engineering ·K. Hamioud, V. Arnal, A. Farcy, V. Jousseaume, A. Zenasni, B. Icard, Jonathan Pradelles, S. Manakli, P. Brun, G. Imbert, C. Jayet, M. Assous, S. Maı̂trejean, D. Galpin, C. Monget, J. Guillan, S. Chhun, E. Richard, D. Barbier, M. Haond	2009	14
15	Demonstration of a Wafer Level Face- To-Back (F2B) Fine Pitch Cu-Cu Hybrid Bonding with High Density TSV for 3D Integration Applications SPIRE - Sciences Po Institutional REpository ·Jerzy Javier Suarez Berru, Stéphane Nicolas, N. Bresson, M. Assous, S. Borel	2023	13
16	High density 3D silicon interposer technology development and electrical characterization for high end applications Jean Charbonnier, M. Assous, Jean-Philippe Bally, Ken Miyairi, Masahiro Sunohara, R. Cuchet, H. Feldis, N. Bouzaida, Nathalie Bernard-Henriques, R. Hida, Thierry Mourier, Gilles Simon, Mitsutoshi Higashi	2012	11
17	Direct Current (Central Plasma Region) Spectrochemical Analysis of Standard Silicate Rocks and Minerals Applied Spectroscopy ·I. B. Brenner, H. Eldad, L. Argov, A. Harel, M. Assous	1975	7
18	Wet or plasma clean? Competing or complementary? A dual damascene study with Si-OC-H dielectric on copper wiring D. Louis, M. Assous, R. Blanc, P. Brun, C. Arvet, E. Lajoinie, D.R. Holmes	2001	7
19	3-layer Fine Pitch Cu-Cu Hybrid Bonding Demonstrator With High Density TSV For Advanced CMOS Image Sensor Applications SPIRE - Sciences Po Institutional REpository ·Stéphane Nicolas, Jerzy-Javier Suarez-Berru, N. Bresson, C. Socquet-Clerc, M. Assous, S. Borel, Rémi Vélard, J. Dechamp, Renan Bouis, Antonio Roman, Karine Abadie, Damien Hebras	2024	7
20	Recent Progress in the Development of High-Density TSV for 3-Layers CMOS Image Sensors SPIRE - Sciences Po Institutional REpository ·S. Borel, M. Assous, S. Moreau, Rémi Vélard	2023	6

About M. Assous

M. Assous is a scholar working on Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Biomedical Engineering, Atomic and Molecular Physics, and Optics and Automotive Engineering, having authored 45 papers that have together received 433 indexed citations. Recurring topics across this work include 3D IC and TSV technologies (28 papers), Copper Interconnects and Reliability (20 papers), Electronic Packaging and Soldering Technologies (20 papers), Semiconductor materials and devices (13 papers), Nanofabrication and Lithography Techniques (5 papers), Advancements in Semiconductor Devices and Circuit Design (4 papers), Semiconductor Lasers and Optical Devices (4 papers) and Photonic and Optical Devices (4 papers). The work is most often cited by research in Electronic, Optical and Magnetic Materials (146 citations), Electrical and Electronic Engineering (401 citations), Mechanics of Materials (60 citations), Automotive Engineering (28 citations) and Hardware and Architecture (14 citations). M. Assous has collaborated with scholars based in France, Japan and Switzerland. Frequent co-authors include A. Farcy, R. Blanc, D. Louis, Jean Charbonnier, S. Borel, L. Arnaud, H. Feldis, O. Louveau, N. Sillon and N. Bresson. Their work appears in journals such as Microelectronic Engineering, MRS Communications, Applied Spectroscopy, IEEE Transactions on Device and Materials Reliability and SPIRE - Sciences Po Institutional REpository.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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