David J. Rennie

707 total citations
17 papers, 537 citations indexed

About

David J. Rennie is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, David J. Rennie has authored 17 papers receiving a total of 537 indexed citations (citations by other indexed papers that have themselves been cited), including 17 papers in Electrical and Electronic Engineering, 8 papers in Hardware and Architecture and 3 papers in Biomedical Engineering. Recurrent topics in David J. Rennie's work include Radiation Effects in Electronics (10 papers), Low-power high-performance VLSI design (10 papers) and VLSI and Analog Circuit Testing (8 papers). David J. Rennie is often cited by papers focused on Radiation Effects in Electronics (10 papers), Low-power high-performance VLSI design (10 papers) and VLSI and Analog Circuit Testing (8 papers). David J. Rennie collaborates with scholars based in Canada, United States and China. David J. Rennie's co-authors include Manoj Sachdev, Shah M. Jahinuzzaman, B. L. Bhuva, S. Jagannathan, Richard Wong, L. W. Massengill, T. D. Loveless, Michael W. McCurdy, Shi-Jie Wen and David Li and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Nuclear Science and IEEE Transactions on Circuits and Systems I Regular Papers.

In The Last Decade

David J. Rennie

17 papers receiving 507 citations

Peers

Countries citing papers authored by David J. Rennie

Since Specialization

Citations

This map shows the geographic impact of David J. Rennie's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by David J. Rennie with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites David J. Rennie more than expected).

Fields of papers citing papers by David J. Rennie

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by David J. Rennie. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by David J. Rennie. The network helps show where David J. Rennie may publish in the future.

Co-authorship network of co-authors of David J. Rennie

This figure shows the co-authorship network connecting the top 25 collaborators of David J. Rennie. A scholar is included among the top collaborators of David J. Rennie based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with David J. Rennie. David J. Rennie is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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17 of 17 papers shown

#	Work	Indexed citations
1	Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS 2012 ·IEEE Transactions on Circuits and Systems I Regular Papers ·David J. Rennie, David Li, Manoj Sachdev, B. L. Bhuva, S. Jagannathan, Shi-Jie Wen, Richard Wong	28
2	Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node 2011 ·IEEE Transactions on Nuclear Science ·T. D. Loveless, S. Jagannathan, (unknown), (unknown), B. L. Bhuva, Michael W. McCurdy, L. W. Massengill, (unknown), Richard Wong, David J. Rennie	105
3	Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS 2011 ·David J. Rennie, David Li, Manoj Sachdev, B. L. Bhuva, S. Jagannathan, Shi-Jie Wen, Rick Wong	6
4	Novel Soft Error Robust Flip-Flops in 65nm CMOS 2011 ·IEEE Transactions on Nuclear Science ·David J. Rennie, Manoj Sachdev	20
5	Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops 2011 ·David Li, David J. Rennie, Pierce Chuang, David Nairn, Manoj Sachdev	15
6	Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology 2011 ·IEEE Transactions on Nuclear Science ·S. Jagannathan, T. D. Loveless, B. L. Bhuva, Shi-Jie Wen, Richard Wong, Manoj Sachdev, David J. Rennie, L. W. Massengill	39
7	Integrated read assist-sense amplifier scheme for high performance embedded SRAMs 2010 ·(unknown), David J. Rennie, Manoj Sachdev	2
8	Soft error robust impulse and TSPC flip-flops in 90nm CMOS 2009 ·Shah M. Jahinuzzaman, David J. Rennie, Manoj Sachdev	8
9	A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability 2009 ·IEEE Transactions on Nuclear Science ·Shah M. Jahinuzzaman, David J. Rennie, Manoj Sachdev	209
10	Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC 2009 ·IEEE Journal of Solid-State Circuits ·Shah M. Jahinuzzaman, (unknown), David J. Rennie, Manoj Sachdev	18
11	Design challenges in nanometric embedded memories 2009 ·David J. Rennie, (unknown), Manoj Sachdev	2
12	A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector 2008 ·IEEE Transactions on Circuits and Systems I Regular Papers ·David J. Rennie, Manoj Sachdev	12
13	A Novel Tri-State Binary Phase Detector 2007 ·David J. Rennie, Manoj Sachdev	6
14	A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors 2007 ·Conference proceedings/Conference proceedings - IEEE Applied Power Electronics Conference and Exposition ·G. Schrom, P. Hazucha, Fabrice Paillet, David J. Rennie, (unknown), Donald S. Gardner, (unknown), Pengju Sun, (unknown), Michael J. Hill, Kaladhar Radhakrishnan, (unknown)	49
15	Low Voltage Buffered Bandgap Reference 2007 ·P. Hazucha, Fabrice Paillet, (unknown), David J. Rennie, G. Schrom, Donald S. Gardner, Ken’ichi Ikeda, (unknown), Tanay Karnik	5
16	Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits 2007 ·David J. Rennie, Manoj Sachdev	10
17	Design and Optimization of Source Coupled Logic in Multi-Gbit/s Clock and Data Recovery Circuits 2003 ·David J. Rennie	3

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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