Xiaoliang Bai
- Electrical and Electronic Engineering top 10%
- Hardware and Architecture top 2%
- Computer Networks and Communications top 10%
- Software
- Automotive Engineering
- Topics
- Low-power high-performance VLSI design (15 papers)VLSI and Analog Circuit Testing (15 papers)VLSI and FPGA Design Techniques (8 papers)
- Cited by
- Hardware and ArchitectureElectrical and Electronic EngineeringComputer Networks and Communications
- Journals
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsIEEE Transactions on ReliabilityJournal of Electronic Testing
- Partner nations
- United StatesUnited KingdomHungary
In The Last Decade
Xiaoliang Bai
20 papers receiving 560 citations
Peers
Comparison fields: 5 of 25
- Electrical and Electronic Engineering 536
- Hardware and Architecture 443
- Computer Networks and Communications 134
- Software 12
- Automotive Engineering 11
Countries citing papers authored by Xiaoliang Bai
This map shows the geographic impact of Xiaoliang Bai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xiaoliang Bai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xiaoliang Bai more than expected).
Fields of papers citing papers by Xiaoliang Bai
This network shows the impact of papers produced by Xiaoliang Bai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xiaoliang Bai. The network helps show where Xiaoliang Bai may publish in the future.
Co-authorship network of co-authors of Xiaoliang Bai
This figure shows the co-authorship network connecting the top 25 collaborators of Xiaoliang Bai. A scholar is included among the top collaborators of Xiaoliang Bai based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Xiaoliang Bai. Xiaoliang Bai is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 1 | |
| 2 | 6 | |
| 3 | 6 | |
| 4 | 1 | |
| 5 | 2 | |
| 6 | 15 | |
| 7 | 6 | |
| 8 | 13 | |
| 9 | 8 | |
| 10 | 65 | |
| 11 | 4 | |
| 12 | 22 | |
| 13 | 113 | |
| 14 | 73 | |
| 15 | 14 | |
| 16 | 5 | |
| 17 | 6 | |
| 18 | 15 | |
| 19 | 56 | |
| 20 | 150 |
About Xiaoliang Bai
Xiaoliang Bai is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Safety, Risk, Reliability and Quality, having authored 21 papers that have together received 592 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (15 papers), VLSI and Analog Circuit Testing (15 papers) and VLSI and FPGA Design Techniques (8 papers). The work is most often cited by research in Hardware and Architecture (443 citations), Electrical and Electronic Engineering (536 citations) and Computer Networks and Communications (134 citations). Xiaoliang Bai has collaborated with scholars based in United States, United Kingdom and Hungary. Frequent co-authors include Sujit Dey, Zhao Yi, S. Dey, Chong Zhao, Philip N. Strenski, Chandu Visweswariah, J. Rajski, Li Chen, Xiaonan Zhang and Chong Zhao. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Reliability and Journal of Electronic Testing.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.