Y. Nakase

521 total citations
30 papers, 399 citations indexed

About

Y. Nakase is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Y. Nakase has authored 30 papers receiving a total of 399 indexed citations (citations by other indexed papers that have themselves been cited), including 28 papers in Electrical and Electronic Engineering, 14 papers in Biomedical Engineering and 7 papers in Hardware and Architecture. Recurrent topics in Y. Nakase's work include Low-power high-performance VLSI design (16 papers), Analog and Mixed-Signal Circuit Design (14 papers) and Advanced DC-DC Converters (6 papers). Y. Nakase is often cited by papers focused on Low-power high-performance VLSI design (16 papers), Analog and Mixed-Signal Circuit Design (14 papers) and Advanced DC-DC Converters (6 papers). Y. Nakase collaborates with scholars based in Japan, United States and Germany. Y. Nakase's co-authors include Hiroshi Makino, K. Mashiko, Hajime Suzuki, Hirofumi Shinohara, Yasumasa Tsukamoto, Makoto Yabuuchi, Koji Nii, Y. Horiba, Shinichi Hirose and Hiroshi Onoda and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEICE Transactions on Electronics and IEE Proceedings - Circuits Devices and Systems.

In The Last Decade

Y. Nakase

27 papers receiving 351 citations

Peers

Y. Nakase
K. Sasaki Japan
I‐Chyn Wey Taiwan
Uming Ko United States
A. Chiba Japan
Yuan‐Hua Chu Taiwan
M. Matsui Japan
Lars Hedrich Germany
Chung-Hsun Huang Taiwan
A. Albicki United States
Debiprasad Priyabrata Acharya India
K. Sasaki Japan
Y. Nakase
Citations per year, relative to Y. Nakase Y. Nakase (= 1×) peers K. Sasaki

Countries citing papers authored by Y. Nakase

Since Specialization
Citations

This map shows the geographic impact of Y. Nakase's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y. Nakase with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y. Nakase more than expected).

Fields of papers citing papers by Y. Nakase

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Y. Nakase. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y. Nakase. The network helps show where Y. Nakase may publish in the future.

Co-authorship network of co-authors of Y. Nakase

This figure shows the co-authorship network connecting the top 25 collaborators of Y. Nakase. A scholar is included among the top collaborators of Y. Nakase based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y. Nakase. Y. Nakase is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Amano, Hideharu, et al.. (2014). Design of a low power NoC router using Marching Memory Through type. 111–118. 5 indexed citations
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Yabuuchi, Makoto, et al.. (2009). A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist. IEICE Technical Report; IEICE Tech. Rep.. 110(9). 13–159. 64 indexed citations
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Sato, H., Koji Nii, Kōji Yoshida, et al.. (2003). A 400MHz 183mW microcontroller in body-tied SOI technology. 1. 110–481. 1 indexed citations
7.
Suzuki, Hajime, et al.. (2002). Leading-zero anticipatory logic for high-speed floating point addition. 589–592. 6 indexed citations
8.
Makino, Hiroshi, et al.. (2002). A 64 bit carry look-ahead CMOS adder using Modified Carry Select. 585–588. 20 indexed citations
9.
Makino, Hiroshi, et al.. (2001). A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE Journal of Solid-State Circuits. 36(2). 249–257. 34 indexed citations
10.
Oklobdzija, Vojin G., et al.. (1997). Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE Journal of Solid-State Circuits. 32(2). 292–292. 5 indexed citations
11.
Makino, Hiroshi, et al.. (1996). A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs). IEICE Transactions on Electronics. 79(4). 530–537. 2 indexed citations
12.
Makino, Hiroshi, et al.. (1996). A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE Journal of Solid-State Circuits. 31(4). 504–513. 2 indexed citations
13.
Makino, Hiroshi, et al.. (1996). An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE Journal of Solid-State Circuits. 31(6). 773–783. 105 indexed citations
14.
Suzuki, Hajime, et al.. (1996). Leading-zero anticipatory logic for high-speed floating point addition. IEEE Journal of Solid-State Circuits. 31(8). 1157–1164. 79 indexed citations
15.
Nakase, Y., et al.. (1996). A High Speed Wide Band SRAM Macro using Complementary Half-Swing Bus Architecture. 384–387. 2 indexed citations
16.
Nakase, Y., Hajime Suzuki, Hiroshi Makino, Hirofumi Shinohara, & K. Mashiko. (1995). A BiCMOS wired-OR logic. IEEE Journal of Solid-State Circuits. 30(6). 622–628. 1 indexed citations
17.
Nakase, Y., et al.. (1991). A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. IEEE Journal of Solid-State Circuits. 26(4). 518–524. 1 indexed citations
18.
Nakase, Y., et al.. (1988). A macro analysis of soft errors in static RAMs. IEEE Journal of Solid-State Circuits. 23(2). 604–605. 1 indexed citations
19.
Kayano, S., et al.. (1987). A double-word-line structure in bipolar ECL random access memory. IEEE Journal of Solid-State Circuits. 22(4). 543–547. 1 indexed citations
20.
Nakase, Y., et al.. (1986). A Double Word Line Structure in ECL RAM. Symposium on VLSI Technology. 75–76. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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