Y. Nakase
About
In The Last Decade
Y. Nakase
27 papers receiving 351 citations
Peers
Comparison fields: 5 of 20
- Electrical and Electronic Engineering 357
- Computational Theory and Mathematics 166
- Biomedical Engineering 115
- Hardware and Architecture 109
- Signal Processing 56
Countries citing papers authored by Y. Nakase
This map shows the geographic impact of Y. Nakase's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y. Nakase with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y. Nakase more than expected).
Fields of papers citing papers by Y. Nakase
This network shows the impact of papers produced by Y. Nakase. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y. Nakase. The network helps show where Y. Nakase may publish in the future.
Co-authorship network of co-authors of Y. Nakase
This figure shows the co-authorship network connecting the top 25 collaborators of Y. Nakase. A scholar is included among the top collaborators of Y. Nakase based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y. Nakase. Y. Nakase is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Title | Journal | Authors | Indexed citations |
|---|---|---|---|---|
| 1 | Design of a low power NoC router using Marching Memory Through type | Hideharu Amano, Y. Nakase et al. | 5 | |
| 2 | On-chip single-inductor dual-output DC-DC boost converter having dual output/input modes for utilizing external power transistor drive and micro-computer controlled MPPT | Y. Nakase, Shinichi Hirose et al. | 1 | |
| 3 | A 0.5V start-up 87% efficiency 0.75mm<sup>2</sup> on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration | Y. Nakase, Shinichi Hirose et al. | 3 | |
| 4 | A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist | IEICE Technical Report; IEICE Tech. Rep. | Makoto Yabuuchi, Koji Nii et al. | 64 |
| 5 | Analysis technique for systematic variation over whole shot and wafer at 45 nm process node | Y. Nakase, Hirofumi Shinohara et al. | 0 | |
| 6 | A 400MHz 183mW microcontroller in body-tied SOI technology | H. Sato, Koji Nii et al. | 1 | |
| 7 | Leading-zero anticipatory logic for high-speed floating point addition | Hajime Suzuki, Y. Nakase et al. | 6 | |
| 8 | A 64 bit carry look-ahead CMOS adder using Modified Carry Select | Hiroshi Makino, Y. Nakase et al. | 20 | |
| 9 | A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree | IEEE Journal of Solid-State Circuits | Hiroshi Makino, Y. Nakase et al. | 34 |
| 10 | Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply] | IEEE Journal of Solid-State Circuits | Vojin G. Oklobdzija, Hisashi Suzuki et al. | 5 |
| 11 | A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs) | IEICE Transactions on Electronics | Hiroshi Makino, Y. Nakase et al. | 2 |
| 12 | A 286 MHz 64-b floating point multiplier with enhanced CG operation | IEEE Journal of Solid-State Circuits | Hiroshi Makino, Hiroaki Suzuki et al. | 2 |
| 13 | An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture | IEEE Journal of Solid-State Circuits | Hiroshi Makino, Y. Nakase et al. | 105 |
| 14 | Leading-zero anticipatory logic for high-speed floating point addition | IEEE Journal of Solid-State Circuits | Hajime Suzuki, Hiroshi Makino et al. | 79 |
| 15 | A High Speed Wide Band SRAM Macro using Complementary Half-Swing Bus Architecture | Y. Nakase et al. | 2 | |
| 16 | A BiCMOS wired-OR logic | IEEE Journal of Solid-State Circuits | Y. Nakase, Hajime Suzuki et al. | 1 |
| 17 | A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing | IEEE Journal of Solid-State Circuits | Y. Nakase, Takahide Ikeda et al. | 1 |
| 18 | A macro analysis of soft errors in static RAMs | IEEE Journal of Solid-State Circuits | Y. Nakase, Keiko Anami et al. | 1 |
| 19 | A double-word-line structure in bipolar ECL random access memory | IEEE Journal of Solid-State Circuits | S. Kayano, Keiko Anami et al. | 1 |
| 20 | A Double Word Line Structure in ECL RAM | Symposium on VLSI Technology | Y. Nakase, Keiko Anami et al. | 1 |
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.