Paul Rosinger

936 citations

30 papers · 714 indexed · h-index 17

Impact in

Hardware and Architecture top 1%
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
Electrical and Electronic Engineering top 10%
- Integrated Circuits and Semiconductor Failure Analysis
- Low-power high-performance VLSI design
- Radiation Effects in Electronics
- VLSI and FPGA Design Techniques
- Advancements in Photolithography Techniques

Papers in

Hardware and Architecture 24
- VLSI and Analog Circuit Testing 22
Electrical and Electronic Engineering 27
- Integrated Circuits and Semiconductor Failure Analysis 17
- Low-power high-performance VLSI design 9
- VLSI and FPGA Design Techniques 7
- Radiation Effects in Electronics 6
- Advancements in Photolithography Techniques 2

Co-authors: Bashir M. Al‐Hashimi Nicola Nicolici B.M. Al-Hashimi Alireza Ejlali Seyed Ghassem Miremadi Krishnendu Chakrabarty Markus Schmitz P.T. Gonciari
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (4 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2 papers)Electronics Letters (2 papers)Journal of Electronic Testing (1 paper)Journal of Low Power Electronics (1 paper)
Partner nations: United Kingdom Canada Iran

In The Last Decade

Paul Rosinger

29 papers receiving 659 citations

Peers

Countries citing papers authored by Paul Rosinger

Since Specialization

Citations

This map shows the geographic impact of Paul Rosinger's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Paul Rosinger with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Paul Rosinger more than expected).

Fields of papers citing papers by Paul Rosinger

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Paul Rosinger. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Paul Rosinger. The network helps show where Paul Rosinger may publish in the future.

Co-authorship network

The 20 scholars most cited alongside Paul Rosinger, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Paul Rosinger Line = papers co-authored together Paul Rosinger links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Alireza Ejlali, Bashir M. Al‐Hashimi, Paul Rosinger, Seyed Ghassem Miremadi, Luca Benini	2009	47
2	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving Journal of Electronic Testing ·Zhiyuan He, Zebo Peng, Petru Eles, Paul Rosinger, Bashir M. Al‐Hashimi	2008	18
3	SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation Rishad Shafik, Paul Rosinger, Bashir M. Al‐Hashimi	2008	26
4	Bridging Fault Test Method With Adaptive Power Management Awareness IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Saqib Khursheed, Urban Ingelsson, Paul Rosinger, Bashir M. Al‐Hashimi, Nouri Bennini	2008	25
5	Rapid Generation of Thermal-Safe Test Schedules arXiv (Cornell University) ·Paul Rosinger, Bashir M. Al‐Hashimi, Krishnendu Chakrabarty	2007	1
6	Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks Design, Automation, and Test in Europe ·Alireza Ejlali, Bashir M. Al‐Hashimi, Paul Rosinger, Seyed Ghassem Miremadi	2007	33
7	Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks Alireza Ejlali, Bashir M. Al‐Hashimi, Paul Rosinger, Seyed Ghassem Miremadi	2007	30
8	Resistive Bridging Faults DFT with Adaptive Power Management Awareness Urban Ingelsson, Paul Rosinger, Dirk Hennesser, Bashir M. Al‐Hashimi, Nouri Bennini	2007	7
9	Fully integrated sub 100ps photon counting platform Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Steve Buckley, S. Bellis, Paul Rosinger, 広鈴木	2007	2
10	Leakage Read Fault in Nanoscale SRAM: Analysis, Test and Diagnosis ePrints Soton (University of Southampton) ·Luigi Dilillo, Hamdani A. (Ade) Sukma, Paul Rosinger, Patrick Girard	2006	3
11	Minimizing Test Power in SRAM through Reduction of Pre-charge Activity ePrints Soton (University of Southampton) ·Luigi Dilillo, Paul Rosinger, Bashir M. Al‐Hashimi, Patrick Girard	2006	9
12	Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Alireza Ejlali, Bashir M. Al‐Hashimi, Markus Schmitz, Paul Rosinger, Seyed Ghassem Miremadi	2006	62
13	Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling 宮野ひろみ, Paul Rosinger, Bashir M. Al‐Hashimi, Krishnendu Chakrabarty	2006	8
14	Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy Alireza Ejlali, Markus Schmitz, Bashir M. Al‐Hashimi, Seyed Ghassem Miremadi, Paul Rosinger	2005	25
15	Minimization of crosstalk noise, delay and power using a modified bus invert technique Design, Automation, and Test in Europe ·Simon Williams, Bashir M. Al‐Hashimi, Paul Rosinger	2004	20
16	Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Paul Rosinger, Bashir M. Al‐Hashimi, Nicola Nicolici	2004	155
17	Scan architecture for shift and capture cycle power reduction Paul Rosinger, B.M. Al-Hashimi, Nicola Nicolici	2003	28
18	Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding Paul Rosinger, B.M. Al-Hashimi, Nicola Nicolici	2003	44
19	Power profile manipulation: a new approach for reducing test application time under power constraints IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Paul Rosinger, Bashir M. Al‐Hashimi, Nicola Nicolici	2002	25
20	Power constrained test scheduling using power profile manipulation Paul Rosinger	2001	10

About Paul Rosinger

Paul Rosinger is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Instrumentation and Bioengineering, having authored 30 papers that have together received 714 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (22 papers), Integrated Circuits and Semiconductor Failure Analysis (17 papers), Low-power high-performance VLSI design (9 papers), VLSI and FPGA Design Techniques (7 papers), Interconnection Networks and Systems (6 papers), Radiation Effects in Electronics (6 papers), Engineering and Test Systems (3 papers) and Advancements in Photolithography Techniques (2 papers). The work is most often cited by research in Hardware and Architecture (606 citations), Electrical and Electronic Engineering (643 citations), Computer Networks and Communications (157 citations), Software (13 citations) and Control and Systems Engineering (61 citations). Paul Rosinger has collaborated with scholars based in United Kingdom, Canada and Iran. Frequent co-authors include Bashir M. Al‐Hashimi, Nicola Nicolici, B.M. Al-Hashimi, Alireza Ejlali, Seyed Ghassem Miremadi, Krishnendu Chakrabarty, Markus Schmitz, P.T. Gonciari, Rishad Shafik and Luca Benini. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Electronics Letters, Journal of Electronic Testing and Journal of Low Power Electronics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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