T. Assis

418 total citations
18 papers, 250 citations indexed

About

T. Assis is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Infectious Diseases. According to data from OpenAlex, T. Assis has authored 18 papers receiving a total of 250 indexed citations (citations by other indexed papers that have themselves been cited), including 18 papers in Electrical and Electronic Engineering, 7 papers in Hardware and Architecture and 0 papers in Infectious Diseases. Recurrent topics in T. Assis's work include Radiation Effects in Electronics (18 papers), Semiconductor materials and devices (9 papers) and Low-power high-performance VLSI design (8 papers). T. Assis is often cited by papers focused on Radiation Effects in Electronics (18 papers), Semiconductor materials and devices (9 papers) and Low-power high-performance VLSI design (8 papers). T. Assis collaborates with scholars based in United States, Israel and Brazil. T. Assis's co-authors include B. L. Bhuva, L. W. Massengill, N. N. Mahatme, Richard Wong, Shi-Jie Wen, N. J. Gaspard, Balaji Narasimham, T. D. Loveless, S. Jagannathan and Dennis R. Ball and has published in prestigious journals such as IEEE Transactions on Nuclear Science, Explore Bristol Research and Science and Technology Facilities Council.

In The Last Decade

T. Assis

18 papers receiving 243 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
T. Assis United States	9	249	135	12	9	4	18	250
Maximilien Glorieux France	10	251 1.0×	112 0.8×	7 0.6×	8 0.9×	11 2.8×	20	254
Tino Heijmen Netherlands	9	305 1.2×	163 1.2×	13 1.1×	3 0.3×	4 1.0×	10	306
T. D. Haeffner United States	12	329 1.3×	123 0.9×	3 0.3×	4 0.4×	6 1.5×	23	335
R.K. Treece United States	9	252 1.0×	163 1.2×	4 0.3×	5 0.6×	4 1.0×	16	259
D. Giot France	9	497 2.0×	269 2.0×	13 1.1×	13 1.4×	13 3.3×	10	501
D.I. Burton United States	9	379 1.5×	40 0.3×	9 0.8×	4 0.4×	1 0.3×	12	380
S. Perrella Italy	4	56 0.2×	38 0.3×	3 0.3×	10 1.1×	10 2.5×	16	69
Varsha Balakrishnan United States	8	312 1.3×	105 0.8×	3 0.3×		15 3.8×	8	321
M. Agostinelli United States	10	400 1.6×	105 0.8×	3 0.3×		15 3.8×	15	408
S. Joshi United States	9	219 0.9×	49 0.4×		4 0.4×	18 4.5×	23	238

Countries citing papers authored by T. Assis

Since Specialization

Citations

This map shows the geographic impact of T. Assis's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by T. Assis with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites T. Assis more than expected).

Fields of papers citing papers by T. Assis

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by T. Assis. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by T. Assis. The network helps show where T. Assis may publish in the future.

Co-authorship network of co-authors of T. Assis

This figure shows the co-authorship network connecting the top 25 collaborators of T. Assis. A scholar is included among the top collaborators of T. Assis based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with T. Assis. T. Assis is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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18 of 18 papers shown

Brockman, John, T. Assis, Xue Fan, et al.. (2017). Thermal neutron-induced soft-error rates for flip-flop designs in 16-nm bulk FinFET technology. 3D–3.1. 9 indexed citations

Assis, T., Dennis R. Ball, Kai Ni, et al.. (2016). Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies. 42. 5C–3. 24 indexed citations

Assis, T., N. N. Mahatme, Balaji Narasimham, et al.. (2016). Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes. IEEE Transactions on Nuclear Science. 64(1). 457–463. 24 indexed citations

Assis, T., J. S. Kauppila, B. L. Bhuva, et al.. (2016). Estimation of single-event transient pulse characteristics for predictive analysis. SE–5. 6 indexed citations

Assis, T., et al.. (2016). Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process. IEEE Transactions on Nuclear Science. 64(1). 477–482. 5 indexed citations

Assis, T., et al.. (2016). Angular Effects of Heavy-Ion Strikes on Single-Event Upset Response of Flip-Flop Designs in 16-nm Bulk FinFET Technology. IEEE Transactions on Nuclear Science. 64(1). 491–496. 28 indexed citations

Mahatme, N. N., et al.. (2016). Impact of particle LET on combinational logic single-event effects for advanced technologies. 2 indexed citations

Assis, T., Dennis R. Ball, Indranil Chatterjee, et al.. (2016). Single-event upset responses of dual- and triple-well designs at advanced planar and FinFET technologies. 1–6. 3 indexed citations

Ball, Dennis R., et al.. (2016). SE performance of a Schmitt-trigger-based D-flip-flop design in a 16-nm bulk FinFET CMOS process. 3B–2. 5 indexed citations

10.

Mahatme, N. N., B. L. Bhuva, N. J. Gaspard, et al.. (2015). Terrestrial SER characterization for nanoscale technologies: A comparative study. Science and Technology Facilities Council. 4B.4.1–4B.4.7. 12 indexed citations

11.

Kauppila, J. S., T. D. Haeffner, T. Assis, et al.. (2015). Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology. IEEE Transactions on Nuclear Science. 62(6). 2613–2619. 17 indexed citations

12.

Assis, T., Kai Ni, J. S. Kauppila, et al.. (2015). Estimation of Single-Event-Induced Collected Charge for Multiple Transistors Using Analytical Expressions. IEEE Transactions on Nuclear Science. 62(6). 2853–2859. 4 indexed citations

13.

Mahatme, N. N., N. J. Gaspard, T. Assis, et al.. (2014). Impact of technology scaling on the combinational logic soft error rate. Explore Bristol Research. 5F.2.1–5F.2.6. 35 indexed citations

14.

Mahatme, N. N., N. J. Gaspard, T. Assis, et al.. (2014). Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors. IEEE Transactions on Nuclear Science. 61(6). 3274–3281. 7 indexed citations

15.

Narasimham, Balaji, et al.. (2014). High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process. 5F.4.1–5F.4.5. 7 indexed citations

16.

Jagannathan, S., T. D. Loveless, B. L. Bhuva, et al.. (2012). Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology. IEEE Transactions on Nuclear Science. 59(6). 2796–2802. 49 indexed citations

17.

Assis, T., Fernanda Lima Kastensmidt, Gilson Wirth, & Ricardo Reis. (2009). Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies. 1. 1–6. 5 indexed citations

18.

Kastensmidt, Fernanda Lima, et al.. (2009). Transistor sizing and folding techniques for radiation hardening. 512–519. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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