Stephen T. Quay

869 total citations
22 papers, 650 citations indexed

About

Stephen T. Quay is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Stephen T. Quay has authored 22 papers receiving a total of 650 indexed citations (citations by other indexed papers that have themselves been cited), including 22 papers in Electrical and Electronic Engineering, 14 papers in Hardware and Architecture and 5 papers in Computer Networks and Communications. Recurrent topics in Stephen T. Quay's work include Low-power high-performance VLSI design (21 papers), VLSI and FPGA Design Techniques (18 papers) and VLSI and Analog Circuit Testing (7 papers). Stephen T. Quay is often cited by papers focused on Low-power high-performance VLSI design (21 papers), VLSI and FPGA Design Techniques (18 papers) and VLSI and Analog Circuit Testing (7 papers). Stephen T. Quay collaborates with scholars based in United States. Stephen T. Quay's co-authors include Charles J. Alpert, Anirudh Devgan, A. Devgan, Jiang Hu, Paul G. Villarrubia, Sachin S. Sapatnekar, C. N. Sze, J.P. Fishburn, Jiang Hu and Gi-Joon Nam and has published in prestigious journals such as Proceedings of the IEEE, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Digital Commons - Michigan Tech (Michigan Technological University).

In The Last Decade

Stephen T. Quay

22 papers receiving 615 citations

Peers

Stephen T. Quay
Paul Rosinger United Kingdom
Gustavo Tèllez United States
Paul S. Zuchowski United States
W.B. Jone United States
Aseem Agarwal United States
P.E. Gronowski United States
Kwok-Shing Leung United States
Kee Sup Kim United States
Stephen T. Quay
Citations per year, relative to Stephen T. Quay Stephen T. Quay (= 1×) peers Desmond A. Kirkpatrick

Countries citing papers authored by Stephen T. Quay

Since Specialization
Citations

This map shows the geographic impact of Stephen T. Quay's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Stephen T. Quay with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Stephen T. Quay more than expected).

Fields of papers citing papers by Stephen T. Quay

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Stephen T. Quay. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Stephen T. Quay. The network helps show where Stephen T. Quay may publish in the future.

Co-authorship network of co-authors of Stephen T. Quay

This figure shows the co-authorship network connecting the top 25 collaborators of Stephen T. Quay. A scholar is included among the top collaborators of Stephen T. Quay based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Stephen T. Quay. Stephen T. Quay is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Li, Zhuo, et al.. (2008). Fast interconnect synthesis with layer assignment. Digital Commons - Michigan Tech (Michigan Technological University). 71–77. 29 indexed citations
2.
Alpert, Charles J., Zhuo Li, Gi-Joon Nam, et al.. (2007). Techniques for Fast Physical Synthesis. Proceedings of the IEEE. 95(3). 573–599. 64 indexed citations
3.
Li, Zhuo, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, & Weiping Shi. (2007). Probabilistic Congestion Prediction with Partial Blockages. 841–846. 8 indexed citations
4.
Alpert, Charles J., Zhuo Li, Gi-Joon Nam, et al.. (2007). The nuts and bolts of physical synthesis. 89–94. 2 indexed citations
5.
Alpert, Charles J., et al.. (2004). Porosity-Aware Buffered Steiner Tree Construction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23(4). 517–526. 10 indexed citations
6.
Alpert, Charles J., et al.. (2004). A fast algorithm for identifying good buffer insertion candidate locations. 47–52. 13 indexed citations
7.
Alpert, Charles J., et al.. (2004). Fast and flexible buffer trees that navigate the physical layout environment. 24–29. 15 indexed citations
8.
Alpert, Charles J., et al.. (2004). Simultaneous Driver Sizing and Buffer Insertion Usinga Delay Penalty Estimation Technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23(1). 136–141. 13 indexed citations
9.
Alpert, Charles J., et al.. (2003). Porosity aware buffered steiner tree construction. 158–165. 10 indexed citations
10.
Hu, Jiang, et al.. (2003). Buffer insertion with adaptive blockage avoidance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22(4). 492–498. 19 indexed citations
11.
Alpert, Charles J., A. Devgan, & Stephen T. Quay. (2003). Buffer insertion with accurate gate and interconnect delay computation. 479–484. 26 indexed citations
12.
Alpert, Charles J., et al.. (2002). Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. 104–109. 8 indexed citations
13.
Alpert, Charles J., et al.. (2002). Buffer library selection. 221–226. 17 indexed citations
14.
Alpert, Charles J., et al.. (2002). Steiner tree optimization for buffers. Blockages and bays. 5. 399–402. 5 indexed citations
15.
Hu, Jiang, et al.. (2002). Buffer insertion with adaptive blockage avoidance. 7 indexed citations
16.
Alpert, Charles J., A. Devgan, J.P. Fishburn, & Stephen T. Quay. (2001). Interconnect synthesis without wire tapering. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20(1). 90–104. 32 indexed citations
17.
Alpert, Charles J., et al.. (2001). Steiner tree optimization for buffers, blockages, and bays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20(4). 556–562. 30 indexed citations
18.
Alpert, Charles J., A. Devgan, & Stephen T. Quay. (1999). Buffer insertion for noise and delay optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18(11). 1633–1645. 86 indexed citations
19.
Alpert, Charles J., Anirudh Devgan, & Stephen T. Quay. (1999). Buffer insertion with accurate gate and interconnect delay computation. 479–484. 92 indexed citations
20.
Alpert, Charles J., Anirudh Devgan, & Stephen T. Quay. (1998). Buffer insertion for noise and delay optimization. 362–367. 114 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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