Stephen T. Quay

869 citations

22 papers · 650 indexed · h-index 14

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing 7
- Parallel Computing and Optimization Techniques 5
- Embedded Systems Design Techniques 4
Electrical and Electronic Engineering top 10%
- Low-power high-performance VLSI design 21
- VLSI and FPGA Design Techniques 18
- Advancements in Semiconductor Devices and Circuit Design 3
- Semiconductor materials and devices 2
Computer Networks and Communications top 5%
- Interconnection Networks and Systems 5
Software
Computational Theory and Mathematics

Co-authors: Charles J. Alpert Anirudh Devgan A. Devgan Jiang Hu Paul G. Villarrubia Sachin S. Sapatnekar C. N. Sze J.P. Fishburn
Cited by: Hardware and Architecture Electrical and Electronic Engineering Computer Networks and Communications
Journals: Proceedings of the IEEE (1 paper)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (6 papers)Digital Commons - Michigan Tech (Michigan Technological University) (1 paper)
Partner nations: United States

In The Last Decade

Stephen T. Quay

22 papers receiving 615 citations

Peers

Countries citing papers authored by Stephen T. Quay

Since Specialization

Citations

This map shows the geographic impact of Stephen T. Quay's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Stephen T. Quay with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Stephen T. Quay more than expected).

Fields of papers citing papers by Stephen T. Quay

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Stephen T. Quay. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Stephen T. Quay. The network helps show where Stephen T. Quay may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Stephen T. Quay, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Stephen T. Quay Line = papers co-authored together Stephen T. Quay links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Fast interconnect synthesis with layer assignment Digital Commons - Michigan Tech (Michigan Technological University) ·Zhuo Li,Charles J. Alpert,Shiyan Hu,Tuhin Muhmud,Stephen T. Quay,Paul G. Villarrubia	2008	29
2	Techniques for Fast Physical Synthesis Proceedings of the IEEE ·Charles J. Alpert,S.K. Karandikar,Zhuo Li,Gi-Joon Nam,Stephen T. Quay,Haoxing Ren,C. N. Sze,Paul G. Villarrubia,Mehmet Yildi̇z	2007	64
3	Probabilistic Congestion Prediction with Partial Blockages Zhuo Li,Charles J. Alpert,Stephen T. Quay,Sachin S. Sapatnekar,Weiping Shi	2007	8
4	The nuts and bolts of physical synthesis Charles J. Alpert,S.K. Karandikar,Zhuo Li,Gi-Joon Nam,Stephen T. Quay,Haoxing Ren,Cliff Sze,Paul G. Villarrubia,Mehmet Yıldız	2007	2
5	Porosity-Aware Buffered Steiner Tree Construction IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Charles J. Alpert,Gopal Gandham,Miloš Hrkić,Jiang Hu,Stephen T. Quay,C. N. Sze	2004	10
6	A fast algorithm for identifying good buffer insertion candidate locations Charles J. Alpert,Miloš Hrkić,Stephen T. Quay	2004	13
7	Fast and flexible buffer trees that navigate the physical layout environment Charles J. Alpert,Miloš Hrkić,Jiang Hu,Stephen T. Quay	2004	15
8	Simultaneous Driver Sizing and Buffer Insertion Usinga Delay Penalty Estimation Technique IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Charles J. Alpert,Chris Chu,Gopal Gandham,Miloš Hrkić,Jiang Hu,Chandramouli Kashyap,Stephen T. Quay	2004	13
9	Porosity aware buffered steiner tree construction Charles J. Alpert,Gopal Gandham,Miloš Hrkić,Jiang Hu,Stephen T. Quay	2003	10
10	Buffer insertion with adaptive blockage avoidance IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Jiang Hu,Charles J. Alpert,Stephen T. Quay,Gopal Gandham	2003	19
11	Buffer insertion with accurate gate and interconnect delay computation Charles J. Alpert,A. Devgan,Stephen T. Quay	2003	26
12	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique Charles J. Alpert,Chris Chu,Gopal Gandham,Miloš Hrkić,Jiang Hu,Chandramouli Kashyap,Stephen T. Quay	2002	8
13	Buffer library selection Charles J. Alpert,Rajesh Gandham,J.L. Neves,Stephen T. Quay	2002	17
14	Steiner tree optimization for buffers. Blockages and bays Charles J. Alpert,Gopal Gandham,Jiang Hu,J.L. Neves,Stephen T. Quay,Sachin S. Sapatnekar	2002	5
15	Buffer insertion with adaptive blockage avoidance Jiang Hu,Charles J. Alpert,Stephen T. Quay,Gopal Gandham	2002	7
16	Interconnect synthesis without wire tapering IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Charles J. Alpert,A. Devgan,J.P. Fishburn,Stephen T. Quay	2001	32
17	Steiner tree optimization for buffers, blockages, and bays IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Charles J. Alpert,Gopal Gandham,Jiang Hu,J.I. Neves,Stephen T. Quay,Sachin S. Sapatnekar	2001	30
18	Buffer insertion for noise and delay optimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Charles J. Alpert,A. Devgan,Stephen T. Quay	1999	86
19	Buffer insertion with accurate gate and interconnect delay computation Charles J. Alpert,Anirudh Devgan,Stephen T. Quay	1999	92
20	Buffer insertion for noise and delay optimization Charles J. Alpert,Anirudh Devgan,Stephen T. Quay	1998	114

About Stephen T. Quay

Stephen T. Quay is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications, having authored 22 papers that have together received 650 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (21 papers), VLSI and FPGA Design Techniques (18 papers), VLSI and Analog Circuit Testing (7 papers), Interconnection Networks and Systems (5 papers), Parallel Computing and Optimization Techniques (5 papers), Embedded Systems Design Techniques (4 papers), Advancements in Semiconductor Devices and Circuit Design (3 papers) and Semiconductor materials and devices (2 papers). The work is most often cited by research in Hardware and Architecture (417 citations), Electrical and Electronic Engineering (619 citations) and Computer Networks and Communications (169 citations). Stephen T. Quay has collaborated with scholars based in United States. Frequent co-authors include Charles J. Alpert, Anirudh Devgan, A. Devgan, Jiang Hu, Paul G. Villarrubia, Sachin S. Sapatnekar, C. N. Sze, J.P. Fishburn, Jiang Hu and Gi-Joon Nam. Their work appears in journals such as Proceedings of the IEEE, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Digital Commons - Michigan Tech (Michigan Technological University).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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