J.P. Fishburn

1.9k total citations · 1 hit paper
29 papers, 967 citations indexed

About

J.P. Fishburn is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, J.P. Fishburn has authored 29 papers receiving a total of 967 indexed citations (citations by other indexed papers that have themselves been cited), including 18 papers in Electrical and Electronic Engineering, 16 papers in Hardware and Architecture and 5 papers in Computer Networks and Communications. Recurrent topics in J.P. Fishburn's work include Low-power high-performance VLSI design (16 papers), VLSI and FPGA Design Techniques (15 papers) and VLSI and Analog Circuit Testing (8 papers). J.P. Fishburn is often cited by papers focused on Low-power high-performance VLSI design (16 papers), VLSI and FPGA Design Techniques (15 papers) and VLSI and Analog Circuit Testing (8 papers). J.P. Fishburn collaborates with scholars based in United States and Germany. J.P. Fishburn's co-authors include A.E. Dunlop, Raphael A. Finkel, Alberto Sangiovanni‐Vincentelli, Catherine A. Schevon, Dwight D. Hill, A. Devgan, Stephen T. Quay, Sachin S. Sapatnekar, Charles J. Alpert and Kurt Keutzer and has published in prestigious journals such as IEEE Transactions on Pattern Analysis and Machine Intelligence, IEEE Journal of Solid-State Circuits and Artificial Intelligence.

In The Last Decade

J.P. Fishburn

26 papers receiving 898 citations

Hit Papers

align trajectories

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
J.P. Fishburn United States	14	807	658	139	107	51	29	967
Clinton W. Kelly United States	10	123 0.2×	90 0.1×	123 0.9×	50 0.5×	16 0.3×	19	296
A. Srinivasan United States	12	402 0.5×	280 0.4×	79 0.6×	46 0.4×	157 3.1×	23	543
M. Suzuoki Japan	7	171 0.2×	344 0.5×	263 1.9×	42 0.4×	54 1.1×	10	495
Takashi Nanya Japan	12	352 0.4×	310 0.5×	254 1.8×	55 0.5×	61 1.2×	94	581
Alfonso Sánchez‐Macián Spain	11	316 0.4×	195 0.3×	189 1.4×	68 0.6×	21 0.4×	57	457
Charles P. Thacker United States	10	615 0.8×	825 1.3×	1.5k 10.6×	61 0.6×	39 0.8×	13	1.6k
Dye-Jyun Ma United States	7	300 0.4×	60 0.1×	119 0.9×	29 0.3×	32 0.6×	17	425
Erich Barke Germany	15	499 0.6×	386 0.6×	33 0.2×	22 0.2×	199 3.9×	94	664
Imran Bashir United States	14	300 0.4×	64 0.1×	45 0.3×	101 0.9×	19 0.4×	45	468
R. V. Levin Russia	10	96 0.1×	235 0.4×	424 3.1×	306 2.9×	38 0.7×	40	692

Countries citing papers authored by J.P. Fishburn

Since Specialization

Citations

This map shows the geographic impact of J.P. Fishburn's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J.P. Fishburn with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J.P. Fishburn more than expected).

Fields of papers citing papers by J.P. Fishburn

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J.P. Fishburn. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J.P. Fishburn. The network helps show where J.P. Fishburn may publish in the future.

Co-authorship network of co-authors of J.P. Fishburn

This figure shows the co-authorship network connecting the top 25 collaborators of J.P. Fishburn. A scholar is included among the top collaborators of J.P. Fishburn based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J.P. Fishburn. J.P. Fishburn is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Fishburn, J.P.. (2018). Search-based opening book construction. ICGA Journal. 40(1). 2–14.

2.

Chakraborty, Kanad, et al.. (2003). A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization. 144. 23–26. 1 indexed citations

3.

Fishburn, J.P.. (2003). LATTIS: an iterative speedup heuristic for mapped logic. 488–491. 5 indexed citations

4.

Dunlop, A.E., et al.. (2003). Experiments using automatic physical design techniques for optimizing circuit performance. 216–220.

5.

Dunlop, A.E., et al.. (2002). Experiments using automatic physical design techniques for optimizing circuit performance. 847–851. 10 indexed citations

6.

Hill, Dwight D., et al.. (2002). A set of switch-level synthesis tools. 2571–2575. 2 indexed citations

7.

Fishburn, J.P. & Sachin Taneja. (2002). Transistor sizing for high performance and low power. 591–594. 1 indexed citations

8.

Fishburn, J.P.. (2002). A depth-decreasing heuristic for combinational logic; or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between. 361–364. 21 indexed citations

9.

Alpert, Charles J., A. Devgan, J.P. Fishburn, & Stephen T. Quay. (2001). Interconnect synthesis without wire tapering. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20(1). 90–104. 32 indexed citations

10.

Fishburn, J.P.. (1997). Shaping a VLSI wire to minimize Elmore delay. 244–251. 24 indexed citations

11.

Sapatnekar, Sachin S., et al.. (1995). Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. International Conference on Computer Aided Design. 17(2). 173–182. 15 indexed citations

12.

Fishburn, J.P.. (1992). LATTIS: an iterative speedup heuristic for mapped logic. Design Automation Conference. 488–491. 26 indexed citations

13.

Sangiovanni‐Vincentelli, Alberto, et al.. (1988). Optimization-based transistor sizing. IEEE Journal of Solid-State Circuits. 23(2). 400–409. 141 indexed citations

14.

Fishburn, J.P., et al.. (1986). A Database-Driven VLSI Design System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 5(1). 180–187. 3 indexed citations

15.

Hill, Dwight D., J.P. Fishburn, & Mary D. P. Leland. (1985). Effective Use of Virtual Grid Compaction in Macro-Module Generators. Design Automation Conference. 777–780. 1 indexed citations

16.

Hill, Dwight D., J.P. Fishburn, & Mary D. P. Leland. (1985). Effective use of virtual grid compaction in macro-module generators. 777–780. 1 indexed citations

17.

Finkel, Raphael A. & J.P. Fishburn. (1983). Improved Speedup Bounds for Parallel Alpha-Beta Search. IEEE Transactions on Pattern Analysis and Machine Intelligence. PAMI-5(1). 89–92. 14 indexed citations

18.

Fishburn, J.P.. (1983). Another optimization of alpha-beta search. ACM SIGART Bulletin. 37–38. 1 indexed citations

19.

Fishburn, J.P., et al.. (1983). Vdd - A VLSI Design Database System.. 25–37. 11 indexed citations

20.

Finkel, Raphael A. & J.P. Fishburn. (1982). Parallelism in alpha-beta search. Artificial Intelligence. 19(1). 89–106. 43 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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