Jiang Hu

5.1k total citations
264 papers, 3.6k citations indexed

About

Jiang Hu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Jiang Hu has authored 264 papers receiving a total of 3.6k indexed citations (citations by other indexed papers that have themselves been cited), including 219 papers in Electrical and Electronic Engineering, 171 papers in Hardware and Architecture and 44 papers in Computer Networks and Communications. Recurrent topics in Jiang Hu's work include Low-power high-performance VLSI design (150 papers), VLSI and FPGA Design Techniques (148 papers) and VLSI and Analog Circuit Testing (95 papers). Jiang Hu is often cited by papers focused on Low-power high-performance VLSI design (150 papers), VLSI and FPGA Design Techniques (148 papers) and VLSI and Analog Circuit Testing (95 papers). Jiang Hu collaborates with scholars based in United States, China and United Kingdom. Jiang Hu's co-authors include Sachin S. Sapatnekar, Charles J. Alpert, Yifang Liu, Yiran Chen, Ganesh Venkataraman, Steven M. Burns, Rabi Mahapatra, Anand Rajaram, Wenbin Xu and C. N. Sze and has published in prestigious journals such as Scientific Reports, IEEE Transactions on Industrial Electronics and Physics in Medicine and Biology.

In The Last Decade

Jiang Hu

247 papers receiving 3.4k citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Jiang Hu United States 32 2.9k 2.0k 693 287 161 264 3.6k
Fadi Kurdahi United States 29 2.1k 0.7× 2.4k 1.2× 1.5k 2.2× 258 0.9× 230 1.4× 254 3.8k
Akash Kumar Germany 32 2.2k 0.7× 2.3k 1.2× 1.7k 2.4× 432 1.5× 248 1.5× 333 4.1k
Dhiraj K. Pradhan United States 35 3.1k 1.1× 2.5k 1.3× 1.9k 2.7× 508 1.8× 72 0.4× 290 4.8k
Ulf Schlichtmann Germany 27 2.8k 1.0× 1.3k 0.7× 314 0.5× 382 1.3× 815 5.1× 356 3.5k
Giovanni Squillero Italy 22 1.1k 0.4× 1.2k 0.6× 160 0.2× 431 1.5× 84 0.5× 157 2.0k
Vincenzo Catania Italy 22 1.1k 0.4× 1.1k 0.6× 1.6k 2.3× 346 1.2× 41 0.3× 182 2.3k
Alex Yakovlev United Kingdom 27 2.5k 0.9× 2.2k 1.1× 1.2k 1.7× 501 1.7× 401 2.5× 498 4.3k
P. Prinetto Italy 26 2.0k 0.7× 2.0k 1.0× 402 0.6× 213 0.7× 24 0.1× 294 2.7k
Davide Rossi Italy 27 1.6k 0.5× 1.0k 0.5× 875 1.3× 547 1.9× 278 1.7× 204 2.9k
Anup Das United States 24 1.4k 0.5× 722 0.4× 593 0.9× 251 0.9× 91 0.6× 116 1.9k

Countries citing papers authored by Jiang Hu

Since Specialization
Citations

This map shows the geographic impact of Jiang Hu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jiang Hu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jiang Hu more than expected).

Fields of papers citing papers by Jiang Hu

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jiang Hu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jiang Hu. The network helps show where Jiang Hu may publish in the future.

Co-authorship network of co-authors of Jiang Hu

This figure shows the co-authorship network connecting the top 25 collaborators of Jiang Hu. A scholar is included among the top collaborators of Jiang Hu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jiang Hu. Jiang Hu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Madhusudan, Meghna, et al.. (2024). MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43(12). 4740–4752. 1 indexed citations
3.
Chen, Xudong, Ying Xu, Shaowei Hu, et al.. (2024). Comprehensive evaluation of dam seepage safety combining deep learning with Dempster-Shafer evidence theory. Measurement. 226. 114172–114172. 4 indexed citations
4.
Pan, Jingyu, et al.. (2023). Toward Fully Automated Machine Learning for Routability Estimator Development. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43(3). 970–982.
5.
Kunal, Kishor, Meghna Madhusudan, Arvind Sharma, et al.. (2023). GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42(9). 2801–2814. 12 indexed citations
6.
Xie, Zhiyao, et al.. (2022). The Dark Side: Security and Reliability Concerns in Machine Learning for EDA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42(4). 1171–1184. 4 indexed citations
7.
Xie, Zhiyao, Rongjian Liang, Xiaoqing Xu, et al.. (2022). Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(11). 4667–4680. 21 indexed citations
8.
Madhusudan, Meghna, et al.. (2022). Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Transactions on Design Automation of Electronic Systems. 28(2). 1–23. 3 indexed citations
9.
Kunal, Kishor, Meghna Madhusudan, Arvind Sharma, et al.. (2020). GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. 55–60. 55 indexed citations
10.
Zhuo, Cheng, et al.. (2019). Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(7). 1498–1510. 63 indexed citations
11.
Hu, Jiang & Cheng‐Kok Koh. (2012). Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design. 6 indexed citations
12.
Özdal, Muhammet Mustafa, Steven M. Burns, & Jiang Hu. (2011). Gate sizing and device technology selection algorithms for high-performance industrial designs. International Conference on Computer Aided Design. 724–731. 35 indexed citations
13.
Chang, Yao‐Wen & Jiang Hu. (2011). Proceedings of the 2011 international symposium on Physical design. 5 indexed citations
14.
Wei, Yaoguang, Jiang Hu, Frank Liu, & Sachin S. Sapatnekar. (2010). Physical design techniques for optimizing RTA-induced variations. Asia and South Pacific Design Automation Conference. 745–750. 2 indexed citations
15.
Li, Peng, et al.. (2007). Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. International Conference on Computer Aided Design. 627–631. 17 indexed citations
16.
Venkataraman, Ganesh, Nikhil Jayakumar, Jiang Hu, et al.. (2005). Practical techniques to reduce skew and its variations in buffered clock networks. International Conference on Computer Aided Design. 592–596. 43 indexed citations
17.
Wu, Di, et al.. (2005). DiCER: distributed and cost-effective redundancy for variation tolerance. International Conference on Computer Aided Design. 393–397. 2 indexed citations
18.
Sze, C. N., Jiang Hu, & Charles J. Alpert. (2004). A place and route aware buffered Steiner tree construction. Asia and South Pacific Design Automation Conference. 355–360. 2 indexed citations
19.
Rajaram, Anand, Bing Lu, Wei Guo, Rabi Mahapatra, & Jiang Hu. (2003). Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. International Conference on Computer Aided Design. 25(9). 401–406. 1 indexed citations
20.
Hu, Jiang & Sachin S. Sapatnekar. (2000). A timing-constrained algorithm for simultaneous global routing of multiple nets. International Conference on Computer Aided Design. 99–103. 46 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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